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b=W3e3QIfi8TSmvsFlnLbzDDqO+hFWldCGfRiXuJxbXVwWdWIUs2UkrJQLWQc323+qaWuy ct3J8wTm047tg69v47EUhsEV1D9tiUPwoTaryL0oig6t/BiWMRe2dX8Rg3ZPxa1SFXgS TW7kNHRe62uY25SZZrqdvA+tzUE0LgpAj7hl8Tv6/62FIgleww0DlDi10Y/7d6w6UgGR FI216E3hbD280ZB44ECjAqkP7dlpLaq5doKGUdZeAHHZ3seCAda45bmZH+Fabj6jve8p Sq/8TVIreGJv7aQbTS58Yn8z+Y7rGpRwcDcbBhJIJLvtoyC0FkvmyvPJI2spVakttrwX jw== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 01/15] spapr: nested: register nested-hv api hcalls only for cap-nested-hv Date: Thu, 18 Jan 2024 10:54:24 +0530 Message-Id: <20240118052438.1475437-2-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Fw5itZoV_xuPzhIIpLN1D_2cryFZtLin X-Proofpoint-ORIG-GUID: ASgI88CYCoCeKJ4M1kuTz3_AfFMQ8WUJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxlogscore=578 lowpriorityscore=0 impostorscore=0 mlxscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555544948100001 Content-Type: text/plain; charset="utf-8" Since cap-nested-hv is an optional capability, it makes sense to register api specfic hcalls only when respective capability is enabled. Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin --- include/hw/ppc/spapr.h | 1 + include/hw/ppc/spapr_nested.h | 1 - hw/ppc/spapr_caps.c | 1 + hw/ppc/spapr_hcall.c | 2 -- hw/ppc/spapr_nested.c | 4 ++-- 5 files changed, 4 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index e91791a1a9..d98fbf1def 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -1025,5 +1025,6 @@ void spapr_vof_client_dt_finalize(SpaprMachineState *= spapr, void *fdt); =20 /* H_WATCHDOG */ void spapr_watchdog_init(SpaprMachineState *spapr); +void spapr_register_nested_hv(void); =20 #endif /* HW_SPAPR_H */ diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index d383486476..41894b24e5 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -96,7 +96,6 @@ struct nested_ppc_state { int64_t tb_offset; }; =20 -void spapr_register_nested(void); void spapr_exit_nested(PowerPCCPU *cpu, int excp); =20 #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index e889244e52..d615be1117 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -487,6 +487,7 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *= spapr, error_append_hint(errp, "Try appending -machine cap-nested-hv= =3Doff " "or use threads=3D1 with -smp\n"); } + spapr_register_nested_hv(); } } =20 diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index fcefd1d1c7..e02f95b840 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1634,8 +1634,6 @@ static void hypercall_register_types(void) spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); =20 spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt); - - spapr_register_nested(); } =20 type_init(hypercall_register_types) diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 121aa96ddc..556d52ddd1 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -375,7 +375,7 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) address_space_unmap(CPU(cpu)->as, regs, len, len, true); } =20 -void spapr_register_nested(void) +void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested); @@ -388,7 +388,7 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) g_assert_not_reached(); } =20 -void spapr_register_nested(void) +void spapr_register_nested_hv(void) { /* DO NOTHING */ } --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555618; cv=none; d=zohomail.com; s=zohoarc; b=VsYwB7BGRrUYJvkBrnQv8BBJOWc3WL5hg7XQwZ1ZEOChxbLRXCPutMuHq4lEQU/IXLZnG4XvYrLQOwPGI4bl9UDPpv1MzRefbhMELtpmeC83r14oO14Opym9w/aVBe66GDB3MIzNoVBLv/SWEzatjzPzSEW+VUQu1Rmn259UVfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555618; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 18 Jan 2024 05:24:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=WT/iFehkVWZA4MvCKi9fT2bCJGVzYXPa0bzPhbsKZE4=; b=F8Qp7Zd2kS2K0qiQuWfRoQZBlWTc2Gjy2g27HkKE8jreswMO0kuezCUdKWin8uFY5h0a diERE2KWytM5YiNe23DNMt71hhUiH4dL/S+Z+rsO6xWEAdkU3N/vuYVPGHinfGFr0ixB T0X+JzD3cfJmt1ZHdlP6TVrlW5LRmQ9dOLPNgmx0dYs6cuK5xlGg7Y6WizJkpAPUwQ4Z VOm75Vujf9I0MYRMbdukJaOpa+JtNSQG4RlAE1Kl8pbiOPF2fo3DZHSK6T6QIAwdpNag 6O51Twly6niUNBRWRyoPw/rGdvMfuLSgf0EhGDu/EsxXQhV7TTW7bDCdR3ocPBrqNyq5 NA== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 02/15] spapr: nested: move nested part of spapr_get_pate into spapr_nested.c Date: Thu, 18 Jan 2024 10:54:25 +0530 Message-Id: <20240118052438.1475437-3-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: cLLQ455IQ1fh2k3e59okUsEEKDfTXbPC X-Proofpoint-ORIG-GUID: Xcxh7kK7nLJgNDKQGOoDU8zAsdUuoy_- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555619001100002 Content-Type: text/plain; charset="utf-8" Most of the nested code has already been moved to spapr_nested.c This logic inside spapr_get_pate is related to nested guests and better suited for spapr_nested.c, hence moving there. Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin --- include/hw/ppc/spapr_nested.h | 3 ++- hw/ppc/spapr.c | 28 ++------------------------- hw/ppc/spapr_nested.c | 36 +++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 27 deletions(-) diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 41894b24e5..cc199a05a7 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -97,5 +97,6 @@ struct nested_ppc_state { }; =20 void spapr_exit_nested(PowerPCCPU *cpu, int excp); - +bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, + target_ulong lpid, ppc_v3_pate_t *entry); #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index e8dabc8614..9e2a42dd2d 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1362,7 +1362,6 @@ void spapr_init_all_lpcrs(target_ulong value, target_= ulong mask) } } =20 - static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) { @@ -1375,33 +1374,10 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vh= yp, PowerPCCPU *cpu, /* Copy PATE1:GR into PATE0:HR */ entry->dw0 =3D spapr->patb_entry & PATE0_HR; entry->dw1 =3D spapr->patb_entry; - + return true; } else { - uint64_t patb, pats; - - assert(lpid !=3D 0); - - patb =3D spapr->nested_ptcr & PTCR_PATB; - pats =3D spapr->nested_ptcr & PTCR_PATS; - - /* Check if partition table is properly aligned */ - if (patb & MAKE_64BIT_MASK(0, pats + 12)) { - return false; - } - - /* Calculate number of entries */ - pats =3D 1ull << (pats + 12 - 4); - if (pats <=3D lpid) { - return false; - } - - /* Grab entry */ - patb +=3D 16 * lpid; - entry->dw0 =3D ldq_phys(CPU(cpu)->as, patb); - entry->dw1 =3D ldq_phys(CPU(cpu)->as, patb + 8); + return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); } - - return true; } =20 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 556d52ddd1..401b52833f 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -6,8 +6,38 @@ #include "hw/ppc/spapr.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/spapr_nested.h" +#include "mmu-book3s-v3.h" =20 #ifdef CONFIG_TCG + +bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, + target_ulong lpid, ppc_v3_pate_t *entry) +{ + uint64_t patb, pats; + + assert(lpid !=3D 0); + + patb =3D spapr->nested_ptcr & PTCR_PATB; + pats =3D spapr->nested_ptcr & PTCR_PATS; + + /* Check if partition table is properly aligned */ + if (patb & MAKE_64BIT_MASK(0, pats + 12)) { + return false; + } + + /* Calculate number of entries */ + pats =3D 1ull << (pats + 12 - 4); + if (pats <=3D lpid) { + return false; + } + + /* Grab entry */ + patb +=3D 16 * lpid; + entry->dw0 =3D ldq_phys(CPU(cpu)->as, patb); + entry->dw1 =3D ldq_phys(CPU(cpu)->as, patb + 8); + return true; +} + #define PRTS_MASK 0x1f =20 static target_ulong h_set_ptbl(PowerPCCPU *cpu, @@ -392,4 +422,10 @@ void spapr_register_nested_hv(void) { /* DO NOTHING */ } + +bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, + target_ulong lpid, ppc_v3_pate_t *entry) +{ + return false; +} #endif --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 18 Jan 2024 05:24:58 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52A9920043; Thu, 18 Jan 2024 05:24:58 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B3F3620040; Thu, 18 Jan 2024 05:24:56 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.in.ibm.com (unknown [9.109.243.35]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 Jan 2024 05:24:56 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=hvo0bkNXkHR5Bbho5x8PJ6EqZsFuex4PXnydnPR1ycU=; b=brRaVIyayC7eF7NIH8LnccvGwNsmPQ5GPKRXsaWZD+WH1fY8BPI7YHLwXdy5Pkw60V/t Fy/X0CFaXlG/RKytzh2daDCGLHOGxKXzkS5t+HY4g17jkHdSr80J7h2OTmHxVGd/9hHw CvohHqllaBPXEBq/HEJQTWN8kobbGZpXKxIGZRYTqQWnfeMdWRdmkBQH5RBeu22QPe0x QgIQGTn/7tV/GLBvwWHVlZgP9ftFJwZjBmNAjUbix3TkEGaxY1VHyXUJpunfH9Uw5PqF UVNZC9AiLbFpH/ItiU0svztkJQMe90B4NGg6FTKbkp7vPlAtBbyePjXPYAXFipo4l/2x Yg== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 03/15] spapr: nested: Introduce SpaprMachineStateNested to store related info. Date: Thu, 18 Jan 2024 10:54:26 +0530 Message-Id: <20240118052438.1475437-4-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: HuHkeCYd60n5rzs4QHeg4vTQ42jLfW7m X-Proofpoint-ORIG-GUID: k6as73qOSFLFWznEyihMff41GfojBcpD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxlogscore=944 lowpriorityscore=0 impostorscore=0 mlxscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555618983100001 Content-Type: text/plain; charset="utf-8" Currently, nested_ptcr is being used by existing nested-hv API to store nested guest related info. This need to be organised to extend support for the nested PAPR API which would need to store additional info related to nested guests in next series of patches. Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin --- include/hw/ppc/spapr.h | 3 ++- include/hw/ppc/spapr_nested.h | 5 +++++ hw/ppc/spapr_nested.c | 8 ++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index d98fbf1def..5521cbe5fb 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -12,6 +12,7 @@ #include "hw/ppc/spapr_xive.h" /* For SpaprXive */ #include "hw/ppc/xics.h" /* For ICSState */ #include "hw/ppc/spapr_tpm_proxy.h" +#include "hw/ppc/spapr_nested.h" /* For SpaprMachineStateNested */ =20 struct SpaprVioBus; struct SpaprPhbState; @@ -213,7 +214,7 @@ struct SpaprMachineState { uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ =20 /* Nested HV support (TCG only) */ - uint64_t nested_ptcr; + SpaprMachineStateNested nested; =20 Notifier epow_notifier; QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index cc199a05a7..e9c11111dd 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -4,6 +4,10 @@ #include "qemu/osdep.h" #include "target/ppc/cpu.h" =20 +typedef struct SpaprMachineStateNested { + uint64_t ptcr; +} SpaprMachineStateNested; + /* * Register state for entering a nested guest with H_ENTER_NESTED. * New member must be added at the end. @@ -97,6 +101,7 @@ struct nested_ppc_state { }; =20 void spapr_exit_nested(PowerPCCPU *cpu, int excp); +typedef struct SpaprMachineState SpaprMachineState; bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry); #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 401b52833f..a41f1af839 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -17,8 +17,8 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, P= owerPCCPU *cpu, =20 assert(lpid !=3D 0); =20 - patb =3D spapr->nested_ptcr & PTCR_PATB; - pats =3D spapr->nested_ptcr & PTCR_PATS; + patb =3D spapr->nested.ptcr & PTCR_PATB; + pats =3D spapr->nested.ptcr & PTCR_PATS; =20 /* Check if partition table is properly aligned */ if (patb & MAKE_64BIT_MASK(0, pats + 12)) { @@ -55,7 +55,7 @@ static target_ulong h_set_ptbl(PowerPCCPU *cpu, return H_PARAMETER; } =20 - spapr->nested_ptcr =3D ptcr; /* Save new partition table */ + spapr->nested.ptcr =3D ptcr; /* Save new partition table */ =20 return H_SUCCESS; } @@ -187,7 +187,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, struct kvmppc_pt_regs *regs; hwaddr len; =20 - if (spapr->nested_ptcr =3D=3D 0) { + if (spapr->nested.ptcr =3D=3D 0) { return H_NOT_AVAILABLE; } =20 --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555631; cv=none; d=zohomail.com; s=zohoarc; b=dfC/rBmB13OZST5KqtxXLytnQUqXuAWP9wYjjWB7xTjGhLCjzfC4/TyZsOLf01f76M0AUbIf/X567zAkjvweJ+Gm9hvLF+9WLoheXIsH2SbQY1OBXvOaBQzf2VNiz9oRinxLjU8wPV15M05WKVnk6YyMWRHgtpz+gk5NbilE8Gg= ARC-Message-Signature: i=1; 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Thu, 18 Jan 2024 05:24:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=fAkrmGFcRyCfiA4GUYgppCJ5SKZIKUEc4xLB43Ulqq8=; b=MC6JPT0TUemOzSQCOA+HqVYpuxVEe/jZGScorZQ6+rbkPRyXq8CzyNEc9xjBLweJM8BV UW/k9zFrX3jNGBgt8vt+Sg03N61Adtr72go5cyBRgI8eP4AXhykd5B5j8E3J7s3xrY6D id2U/pTJUB6+ZCKu0Qnxe1ib3fmodyKvEfAybFsp9Zlca/cc5erSipfagL4TammwbwBO KBr+CuZr8m/2GgxtPMLb0ZGYmmuJR4599X5gGov1uEZyf1M9S6ovRE2T4OOw6LylQkUs qtFjDK/vk8rZQmuucgvqAfKWlwKnRxlXCQ+lvvtubOoqzxsT8ecZFfZdXDeE3DdMsosv PQ== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 04/15] spapr: nested: keep nested-hv related code restricted to its API. Date: Thu, 18 Jan 2024 10:54:27 +0530 Message-Id: <20240118052438.1475437-5-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: f2YtoCy4NW_Cf6KiFlqoiNmYxn3m7CVn X-Proofpoint-GUID: aDzNVP9R-5EKo13u8eqcgTgYNbN4NPMS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 spamscore=0 malwarescore=0 mlxlogscore=780 mlxscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555633063100002 Content-Type: text/plain; charset="utf-8" spapr_exit_nested and spapr_get_pate_nested_hv contains code which is specific to nested-hv API. Isolating code flows based on API helps extending it to be used with different API as well. Signed-off-by: Harsh Prateek Bora Suggested-by: Nicholas Piggin --- include/hw/ppc/spapr_nested.h | 4 ++++ hw/ppc/spapr.c | 7 ++++++- hw/ppc/spapr_caps.c | 1 + hw/ppc/spapr_nested.c | 27 ++++++++++++++++++++++++--- 4 files changed, 35 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index e9c11111dd..28a102c273 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -6,6 +6,8 @@ =20 typedef struct SpaprMachineStateNested { uint64_t ptcr; + uint8_t api; +#define NESTED_API_KVM_HV 1 } SpaprMachineStateNested; =20 /* @@ -104,4 +106,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp); typedef struct SpaprMachineState SpaprMachineState; bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry); +void spapr_nested_init(SpaprMachineState *spapr); +uint8_t spapr_nested_api(SpaprMachineState *spapr); #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 9e2a42dd2d..367beb5255 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1376,7 +1376,11 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhy= p, PowerPCCPU *cpu, entry->dw1 =3D spapr->patb_entry; return true; } else { - return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); + assert(spapr_nested_api(spapr)); + if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { + return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); + } + return false; } } =20 @@ -3451,6 +3455,7 @@ static void spapr_instance_init(Object *obj) spapr_get_host_serial, spapr_set_host_serial); object_property_set_description(obj, "host-serial", "Host serial number to advertise in guest device tree"); + spapr_nested_init(spapr); } =20 static void spapr_machine_finalizefn(Object *obj) diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index d615be1117..c3c83f6e68 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -487,6 +487,7 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *= spapr, error_append_hint(errp, "Try appending -machine cap-nested-hv= =3Doff " "or use threads=3D1 with -smp\n"); } + spapr->nested.api =3D NESTED_API_KVM_HV; spapr_register_nested_hv(); } } diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index a41f1af839..afadd5b22d 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -8,6 +8,16 @@ #include "hw/ppc/spapr_nested.h" #include "mmu-book3s-v3.h" =20 +void spapr_nested_init(SpaprMachineState *spapr) +{ + spapr->nested.api =3D 0; +} + +uint8_t spapr_nested_api(SpaprMachineState *spapr) +{ + return spapr->nested.api; +} + #ifdef CONFIG_TCG =20 bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, @@ -302,7 +312,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, return env->gpr[3]; } =20 -void spapr_exit_nested(PowerPCCPU *cpu, int excp) +static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp) { CPUPPCState *env =3D &cpu->env; SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); @@ -314,8 +324,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) struct kvmppc_pt_regs *regs; hwaddr len; =20 - assert(spapr_cpu->in_nested); - nested_save_state(&l2_state, cpu); hsrr0 =3D env->spr[SPR_HSRR0]; hsrr1 =3D env->spr[SPR_HSRR1]; @@ -405,6 +413,19 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) address_space_unmap(CPU(cpu)->as, regs, len, len, true); } =20 +void spapr_exit_nested(PowerPCCPU *cpu, int excp) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + assert(spapr_cpu->in_nested); + if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { + spapr_exit_nested_hv(cpu, excp); + } else { + g_assert_not_reached(); + } +} + void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555665; cv=none; d=zohomail.com; s=zohoarc; b=ZvjCH9g6T0vmecHd/TD4yNGhom5/YnoIcy859JfeP18wqgSL+eM+8Jc++MiIL5qHoCouLcxmYov+w4a8/JKQA8v8D12EDFv/DGAOwVfq/ZoTJljsNC62iBx9CQx0aG51gTZu9kUMm0JAckICml9JP0XIA8AF87dLqQrzkq/xo38= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555665; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 18 Jan 2024 05:25:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pp1; bh=5IrHtPsYX9wdFKbxZNtjx/Xpvv3e6f3slbo8RoyqlzA=; b=UBxRX5ErED9ocsrXPVhc5WmQsD3025RVX77GxRxIiX5t8PWelivU0z8TZXqO6TwU4OxV vUHEckNnvqNCcHmTukFNEaFHbnYnIlsj89MctuHRqhp9EzsbygArMtsjsu365R9slj6T ETbvA8SdF6MLb12wLoFe7i1QPgi0TlhnJ84n8mdgloyeI3ISN0ZA9THUGx2sUnUZ54Ck qGB4R2OtWeo9Fj12iakuQDftC0QMPKBR0cWexG1IkHCgcN/eK8DoLkGCXCBVkCnyUQ4r YB44CwKQHXqW75EfER0Bn6jDYdrXA+oKRAj20wRUYwZ7q2B7uJowN3IX9GP5Vg6ZvHOj wQ== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 05/15] spapr: nested: Document Nested PAPR API Date: Thu, 18 Jan 2024 10:54:28 +0530 Message-Id: <20240118052438.1475437-6-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: PB8DwQb_rEpyeK4ZhOqkVmLPvmIvTptw X-Proofpoint-ORIG-GUID: yh_L8F4qR_yL6RqZ0jmgkqUYiGXXr5_L Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555667341100003 Content-Type: text/plain; charset="utf-8" Adding initial documentation about Nested PAPR API to describe the set of APIs and its usage. Also talks about the Guest State Buffer elements and it's format which is used between L0/L1 to communicate L2 state. Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora --- docs/devel/nested-papr.txt | 500 +++++++++++++++++++++++++++++++++++++ 1 file changed, 500 insertions(+) create mode 100644 docs/devel/nested-papr.txt diff --git a/docs/devel/nested-papr.txt b/docs/devel/nested-papr.txt new file mode 100644 index 0000000000..3884794296 --- /dev/null +++ b/docs/devel/nested-papr.txt @@ -0,0 +1,500 @@ +Nested PAPR API (aka KVM on PowerVM) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This API aims at providing support to enable nested virtualization with +KVM on PowerVM. While the existing support for nested KVM on PowerNV was +introduced with cap-nested-hv option, however, with a slight design change, +to enable this on papr/pseries, a new cap-nested-papr option is added. eg: + + qemu-system-ppc64 -cpu POWER10 -machine pseries,cap-nested-papr=3Dtrue .= .. + +Work by: + Michael Neuling + Vaibhav Jain + Jordan Niethe + Harsh Prateek Bora + Shivaprasad G Bhat + Kautuk Consul + +Below taken from the kernel documentation: + +Introduction +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This document explains how a guest operating system can act as a +hypervisor and run nested guests through the use of hypercalls, if the +hypervisor has implemented them. The terms L0, L1, and L2 are used to +refer to different software entities. L0 is the hypervisor mode entity +that would normally be called the "host" or "hypervisor". L1 is a +guest virtual machine that is directly run under L0 and is initiated +and controlled by L0. L2 is a guest virtual machine that is initiated +and controlled by L1 acting as a hypervisor. A significant design change +wrt existing API is that now the entire L2 state is maintained within L0. + +Existing Nested-HV API +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Linux/KVM has had support for Nesting as an L0 or L1 since 2018 + +The L0 code was added:: + + commit 8e3f5fc1045dc49fd175b978c5457f5f51e7a2ce + Author: Paul Mackerras + Date: Mon Oct 8 16:31:03 2018 +1100 + KVM: PPC: Book3S HV: Framework and hcall stubs for nested virtualization + +The L1 code was added:: + + commit 360cae313702cdd0b90f82c261a8302fecef030a + Author: Paul Mackerras + Date: Mon Oct 8 16:31:04 2018 +1100 + KVM: PPC: Book3S HV: Nested guest entry via hypercall + +This API works primarily using a signal hcall h_enter_nested(). This +call made by the L1 to tell the L0 to start an L2 vCPU with the given +state. The L0 then starts this L2 and runs until an L2 exit condition +is reached. Once the L2 exits, the state of the L2 is given back to +the L1 by the L0. The full L2 vCPU state is always transferred from +and to L1 when the L2 is run. The L0 doesn't keep any state on the L2 +vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2 +-> L1 exit). + +The only state kept by the L0 is the partition table. The L1 registers +it's partition table using the h_set_partition_table() hcall. All +other state held by the L0 about the L2s is cached state (such as +shadow page tables). + +The L1 may run any L2 or vCPU without first informing the L0. It +simply starts the vCPU using h_enter_nested(). The creation of L2s and +vCPUs is done implicitly whenever h_enter_nested() is called. + +In this document, we call this existing API the v1 API. + +New PAPR API +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The new PAPR API changes from the v1 API such that the creating L2 and +associated vCPUs is explicit. In this document, we call this the v2 +API. + +h_enter_nested() is replaced with H_GUEST_VCPU_RUN(). Before this can +be called the L1 must explicitly create the L2 using h_guest_create() +and any associated vCPUs() created with h_guest_create_vCPU(). Getting +and setting vCPU state can also be performed using h_guest_{g|s}et +hcall. + +The basic execution flow is for an L1 to create an L2, run it, and +delete it is: + +- L1 and L0 negotiate capabilities with H_GUEST_{G,S}ET_CAPABILITIES() + (normally at L1 boot time). + +- L1 requests the L0 to create an L2 with H_GUEST_CREATE() and receives a = token + +- L1 requests the L0 to create an L2 vCPU with H_GUEST_CREATE_VCPU() + +- L1 and L0 communicate the vCPU state using the H_GUEST_{G,S}ET() hcall + +- L1 requests the L0 to run the vCPU using H_GUEST_RUN_VCPU() hcall + +- L1 deletes L2 with H_GUEST_DELETE() + +More details of the individual hcalls follows: + +HCALL Details +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This documentation is provided to give an overall understating of the +API. It doesn't aim to provide full details required to implement +an L1 or L0. Latest PAPR spec shall be referred for more details. + +All these HCALLs are made by the L1 to the L0. + +H_GUEST_GET_CAPABILITIES() +-------------------------- + +This is called to get the capabilities of the L0 nested +hypervisor. This includes capabilities such the CPU versions (eg +POWER9, POWER10) that are supported as L2s. + +H_GUEST_SET_CAPABILITIES() +-------------------------- + +This is called to inform the L0 of the capabilities of the L1 +hypervisor. The set of flags passed here are the same as +H_GUEST_GET_CAPABILITIES() + +Typically, GET will be called first and then SET will be called with a +subset of the flags returned from GET. This process allows the L0 and +L1 to negotiate a agreed set of capabilities. + +H_GUEST_CREATE() +---------------- + +This is called to create a L2. Returned is ID of the L2 created +(similar to an LPID), which can be use on subsequent HCALLs to +identify the L2. + +H_GUEST_CREATE_VCPU() +--------------------- + +This is called to create a vCPU associated with a L2. The L2 id +(returned from H_GUEST_CREATE()) should be passed it. Also passed in +is a unique (for this L2) vCPUid. This vCPUid is allocated by the +L1. + +H_GUEST_SET_STATE() +------------------- + +This is called to set L2 wide or vCPU specific L2 state. This info is +passed via the Guest State Buffer (GSB), details below. + +This can set either L2 wide or vcpu specific information. Examples of +L2 wide is the timebase offset or process scoped page table +info. Examples of vCPU wide are GPRs or VSRs. A bit in the flags +parameter specifies if this call is L2 wide or vCPU specific and the +IDs in the GSB must match this. + +The L1 provides a pointer to the GSB as a parameter to this call. Also +provided is the L2 and vCPU IDs associated with the state to set. + +The L1 writes all values in the GSB and the L0 only reads the GSB for +this call + +H_GUEST_GET_STATE() +------------------- + +This is called to get state associated with a L2 or L2 vCPU. This info +passed via the GSB (details below). + +This can get either L2 wide or vcpu specific information. Examples of +L2 wide is the timebase offset or process scoped page table +info. Examples of vCPU wide are GPRs or VSRs. A bit in the flags +parameter specifies if this call is L2 wide or vCPU specific and the +IDs in the GSB must match this. + +The L1 provides a pointer to the GSB as a parameter to this call. Also +provided is the L2 and vCPU IDs associated with the state to get. + +The L1 writes only the IDs and sizes in the GSB. L0 writes the +associated values for each ID in the GSB. + +H_GUEST_RUN_VCPU() +------------------ + +This is called to run an L2 vCPU. The L2 and vCPU IDs are passed in as +parameters. The vCPU runs with the state set previously using +H_GUEST_SET_STATE(). When the L2 exits, the L1 will resume from this +hcall. + +This hcall also has associated input and output GSBs. Unlike +H_GUEST_{S,G}ET_STATE(), these GSB pointers are not passed in as +parameters to the hcall (This was done in the interest of +performance). The locations of these GSBs must be preregistered using +the H_GUEST_SET_STATE() call with ID 0x0c00 and 0x0c01 (see table later +below). + +The input GSB may contain only VCPU wide elements to be set. This GSB +may also contain zero elements (ie 0 in the first 4 bytes of the GSB) +if nothing needs to be set. + +On exit from the hcall, the output buffer is filled with elements +determined by the L0. The reason for the exit is contained in GPR4 (ie +NIP is put in GPR4). The elements returned depend on the exit +type. For example, if the exit reason is the L2 doing a hcall (GPR4 =3D +0xc00), then GPR3-12 are provided in the output GSB as this is the +state likely needed to service the hcall. If additional state is +needed, H_GUEST_GET_STATE() may be called by the L1. + +To synthesize interrupts in the L2, when calling H_GUEST_RUN_VCPU() +the L1 may set a flag (as a hcall parameter) and the L0 will +synthesize the interrupt in the L2. Alternatively, the L1 may +synthesize the interrupt itself using H_GUEST_SET_STATE() or the +H_GUEST_RUN_VCPU() input GSB to set the state appropriately. + +H_GUEST_DELETE() +---------------- + +This is called to delete an L2. All associated vCPUs are also +deleted. No specific vCPU delete call is provided. + +A flag may be provided to delete all guests. This is used to reset the +L0 in the case of kdump/kexec. + +Guest State Buffer (GSB) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The Guest State Buffer (GSB) is the main method of communicating state +about the L2 between the L1 and L0 via H_GUEST_{G,S}ET() and +H_GUEST_VCPU_RUN() calls. + +State may be associated with a whole L2 (eg timebase offset) or a +specific L2 vCPU (eg. GPR state). Only L2 VCPU state maybe be set by +H_GUEST_VCPU_RUN(). + +All data in the GSB is big endian (as is standard in PAPR) + +The Guest state buffer has a header which gives the number of +elements, followed by the GSB elements themselves. + +GSB header: + ++----------+----------+-------------------------------------------+ +| Offset | Size | Purpose | +| Bytes | Bytes | | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| 0 | 4 | Number of elements | ++----------+----------+-------------------------------------------+ +| 4 | | Guest state buffer elements | ++----------+----------+-------------------------------------------+ + +GSB element: + ++----------+----------+-------------------------------------------+ +| Offset | Size | Purpose | +| Bytes | Bytes | | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| 0 | 2 | ID | ++----------+----------+-------------------------------------------+ +| 2 | 2 | Size of Value | ++----------+----------+-------------------------------------------+ +| 4 | As above | Value | ++----------+----------+-------------------------------------------+ + +The ID in the GSB element specifies what is to be set. This includes +archtected state like GPRs, VSRs, SPRs, plus also some meta data about +the partition like the timebase offset and partition scoped page +table information. + ++--------+-------+----+--------+----------------------------------+ +| ID | Size | RW | Thread | Details | +| | Bytes | | Guest | | +| | | | Scope | | ++=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D+=3D=3D=3D=3D= =3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| 0x0000 | | RW | TG | NOP element | ++--------+-------+----+--------+----------------------------------+ +| 0x0001 | 0x08 | R | G | Size of L0 vCPU state | ++--------+-------+----+--------+----------------------------------+ +| 0x0002 | 0x08 | R | G | Size Run vCPU out buffer | ++--------+-------+----+--------+----------------------------------+ +| 0x0003 | 0x04 | RW | G | Logical PVR | ++--------+-------+----+--------+----------------------------------+ +| 0x0004 | 0x08 | RW | G | TB Offset (L1 relative) | ++--------+-------+----+--------+----------------------------------+ +| 0x0005 | 0x18 | RW | G |Partition scoped page tbl info: | +| | | | | | +| | | | |- 0x00 Addr part scope table | +| | | | |- 0x08 Num addr bits | +| | | | |- 0x10 Size root dir | ++--------+-------+----+--------+----------------------------------+ +| 0x0006 | 0x10 | RW | G |Process Table Information: | +| | | | | | +| | | | |- 0x0 Addr proc scope table | +| | | | |- 0x8 Table size. | ++--------+-------+----+--------+----------------------------------+ +| 0x0007-| | | | Reserved | +| 0x0BFF | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x0C00 | 0x10 | RW | T |Run vCPU Input Buffer: | +| | | | | | +| | | | |- 0x0 Addr of buffer | +| | | | |- 0x8 Buffer Size. | ++--------+-------+----+--------+----------------------------------+ +| 0x0C01 | 0x10 | RW | T |Run vCPU Output Buffer: | +| | | | | | +| | | | |- 0x0 Addr of buffer | +| | | | |- 0x8 Buffer Size. | ++--------+-------+----+--------+----------------------------------+ +| 0x0C02 | 0x08 | RW | T | vCPU VPA Address | ++--------+-------+----+--------+----------------------------------+ +| 0x0C03-| | | | Reserved | +| 0x0FFF | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x1000-| 0x08 | RW | T | GPR 0-31 | +| 0x101F | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x1020 | 0x08 | T | T | HDEC expiry TB | ++--------+-------+----+--------+----------------------------------+ +| 0x1021 | 0x08 | RW | T | NIA | ++--------+-------+----+--------+----------------------------------+ +| 0x1022 | 0x08 | RW | T | MSR | ++--------+-------+----+--------+----------------------------------+ +| 0x1023 | 0x08 | RW | T | LR | ++--------+-------+----+--------+----------------------------------+ +| 0x1024 | 0x08 | RW | T | XER | ++--------+-------+----+--------+----------------------------------+ +| 0x1025 | 0x08 | RW | T | CTR | ++--------+-------+----+--------+----------------------------------+ +| 0x1026 | 0x08 | RW | T | CFAR | ++--------+-------+----+--------+----------------------------------+ +| 0x1027 | 0x08 | RW | T | SRR0 | ++--------+-------+----+--------+----------------------------------+ +| 0x1028 | 0x08 | RW | T | SRR1 | ++--------+-------+----+--------+----------------------------------+ +| 0x1029 | 0x08 | RW | T | DAR | ++--------+-------+----+--------+----------------------------------+ +| 0x102A | 0x08 | RW | T | DEC expiry TB | ++--------+-------+----+--------+----------------------------------+ +| 0x102B | 0x08 | RW | T | VTB | ++--------+-------+----+--------+----------------------------------+ +| 0x102C | 0x08 | RW | T | LPCR | ++--------+-------+----+--------+----------------------------------+ +| 0x102D | 0x08 | RW | T | HFSCR | ++--------+-------+----+--------+----------------------------------+ +| 0x102E | 0x08 | RW | T | FSCR | ++--------+-------+----+--------+----------------------------------+ +| 0x102F | 0x08 | RW | T | FPSCR | ++--------+-------+----+--------+----------------------------------+ +| 0x1030 | 0x08 | RW | T | DAWR0 | ++--------+-------+----+--------+----------------------------------+ +| 0x1031 | 0x08 | RW | T | DAWR1 | ++--------+-------+----+--------+----------------------------------+ +| 0x1032 | 0x08 | RW | T | CIABR | ++--------+-------+----+--------+----------------------------------+ +| 0x1033 | 0x08 | RW | T | PURR | ++--------+-------+----+--------+----------------------------------+ +| 0x1034 | 0x08 | RW | T | SPURR | ++--------+-------+----+--------+----------------------------------+ +| 0x1035 | 0x08 | RW | T | IC | ++--------+-------+----+--------+----------------------------------+ +| 0x1036-| 0x08 | RW | T | SPRG 0-3 | +| 0x1039 | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x103A | 0x08 | W | T | PPR | ++--------+-------+----+--------+----------------------------------+ +| 0x103B | 0x08 | RW | T | MMCR 0-3 | +| 0x103E | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x103F | 0x08 | RW | T | MMCRA | ++--------+-------+----+--------+----------------------------------+ +| 0x1040 | 0x08 | RW | T | SIER | ++--------+-------+----+--------+----------------------------------+ +| 0x1041 | 0x08 | RW | T | SIER 2 | ++--------+-------+----+--------+----------------------------------+ +| 0x1042 | 0x08 | RW | T | SIER 3 | ++--------+-------+----+--------+----------------------------------+ +| 0x1043 | 0x08 | RW | T | BESCR | ++--------+-------+----+--------+----------------------------------+ +| 0x1044 | 0x08 | RW | T | EBBHR | ++--------+-------+----+--------+----------------------------------+ +| 0x1045 | 0x08 | RW | T | EBBRR | ++--------+-------+----+--------+----------------------------------+ +| 0x1046 | 0x08 | RW | T | AMR | ++--------+-------+----+--------+----------------------------------+ +| 0x1047 | 0x08 | RW | T | IAMR | ++--------+-------+----+--------+----------------------------------+ +| 0x1048 | 0x08 | RW | T | AMOR | ++--------+-------+----+--------+----------------------------------+ +| 0x1049 | 0x08 | RW | T | UAMOR | ++--------+-------+----+--------+----------------------------------+ +| 0x104A | 0x08 | RW | T | SDAR | ++--------+-------+----+--------+----------------------------------+ +| 0x104B | 0x08 | RW | T | SIAR | ++--------+-------+----+--------+----------------------------------+ +| 0x104C | 0x08 | RW | T | DSCR | ++--------+-------+----+--------+----------------------------------+ +| 0x104D | 0x08 | RW | T | TAR | ++--------+-------+----+--------+----------------------------------+ +| 0x104E | 0x08 | RW | T | DEXCR | ++--------+-------+----+--------+----------------------------------+ +| 0x104F | 0x08 | RW | T | HDEXCR | ++--------+-------+----+--------+----------------------------------+ +| 0x1050 | 0x08 | RW | T | HASHKEYR | ++--------+-------+----+--------+----------------------------------+ +| 0x1051 | 0x08 | RW | T | HASHPKEYR | ++--------+-------+----+--------+----------------------------------+ +| 0x1052 | 0x08 | RW | T | CTRL | ++--------+-------+----+--------+----------------------------------+ +| 0x1053-| | | | Reserved | +| 0x1FFF | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x2000 | 0x04 | RW | T | CR | ++--------+-------+----+--------+----------------------------------+ +| 0x2001 | 0x04 | RW | T | PIDR | ++--------+-------+----+--------+----------------------------------+ +| 0x2002 | 0x04 | RW | T | DSISR | ++--------+-------+----+--------+----------------------------------+ +| 0x2003 | 0x04 | RW | T | VSCR | ++--------+-------+----+--------+----------------------------------+ +| 0x2004 | 0x04 | RW | T | VRSAVE | ++--------+-------+----+--------+----------------------------------+ +| 0x2005 | 0x04 | RW | T | DAWRX0 | ++--------+-------+----+--------+----------------------------------+ +| 0x2006 | 0x04 | RW | T | DAWRX1 | ++--------+-------+----+--------+----------------------------------+ +| 0x2007-| 0x04 | RW | T | PMC 1-6 | +| 0x200c | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x200D | 0x04 | RW | T | WORT | ++--------+-------+----+--------+----------------------------------+ +| 0x200E | 0x04 | RW | T | PSPB | ++--------+-------+----+--------+----------------------------------+ +| 0x200F-| | | | Reserved | +| 0x2FFF | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x3000-| 0x10 | RW | T | VSR 0-63 | +| 0x303F | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0x3040-| | | | Reserved | +| 0xEFFF | | | | | ++--------+-------+----+--------+----------------------------------+ +| 0xF000 | 0x08 | R | T | HDAR | ++--------+-------+----+--------+----------------------------------+ +| 0xF001 | 0x04 | R | T | HDSISR | ++--------+-------+----+--------+----------------------------------+ +| 0xF002 | 0x04 | R | T | HEIR | ++--------+-------+----+--------+----------------------------------+ +| 0xF003 | 0x08 | R | T | ASDR | ++--------+-------+----+--------+----------------------------------+ + +Miscellaneous info +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +State not in ptregs/hvregs +-------------------------- + +In the v1 API, some state is not in the ptregs/hvstate. This includes +the vector register and some SPRs. For the L1 to set this state for +the L2, the L1 loads up these hardware registers before the +h_enter_nested() call and the L0 ensures they end up as the L2 state +(by not touching them). + +The v2 API removes this and explicitly sets this state via the GSB. + +L1 Implementation details: Caching state +---------------------------------------- + +In the v1 API, all state is sent from the L1 to the L0 and vice versa +on every h_enter_nested() hcall. If the L0 is not currently running +any L2s, the L0 has no state information about them. The only +exception to this is the location of the partition table, registered +via h_set_partition_table(). + +The v2 API changes this so that the L0 retains the L2 state even when +it's vCPUs are no longer running. This means that the L1 only needs to +communicate with the L0 about L2 state when it needs to modify the L2 +state, or when it's value is out of date. This provides an opportunity +for performance optimisation. + +When a vCPU exits from a H_GUEST_RUN_VCPU() call, the L1 internally +marks all L2 state as invalid. This means that if the L1 wants to know +the L2 state (say via a kvm_get_one_reg() call), it needs to call +H_GUEST_GET_STATE() to get that state. Once it's read, it's marked as +valid in L1 until the L2 is run again. + +Also, when an L1 modifies L2 vcpu state, it doesn't need to write it +to the L0 until that L2 vcpu runs again. Hence when the L1 updates +state (say via a kvm_set_one_reg() call), it writes to an internal L1 +copy and only flushes this copy to the L0 when the L2 runs again via +the H_GUEST_VCPU_RUN() input buffer. + +This lazy updating of state by the L1 avoids unnecessary +H_GUEST_{G|S}ET_STATE() calls. + +References +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +For more details, please refer: + +[1] Kernel documentation (patches accepted upstream): + https://lore.kernel.org/linuxppc-dev/169528846875.874757.8861595746180= 557787.b4-ty@ellerman.id.au/ --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555649; cv=none; d=zohomail.com; s=zohoarc; b=QmO1vk3pC0qtscvw7pJIw2RW3uIMW0J875FgT2dJXv508KykNx0vlVGYxg4HTefLKgGP4gJNMdA/KhrdBstM6kykubSWqSHnyndYPBthQqTNTxwkAT+Qz/lSbTEguYSa3PPRG37jmGrzmjj1rFna0/Y+OqiH8hsBZEcsdYI+Eis= ARC-Message-Signature: i=1; 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Thu, 18 Jan 2024 05:25:02 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=/95Wmcn93f21kS2fdFqShZfd28Icl3WRmQGJdtid+9o=; b=Q30tBdVtwPQ3cUsPthTl+1ljidzwRCdMJWWwnQfHxyNdbAWfnCvsK1l6/P22flxWTwUx Am1mNvAHe3LsLI48PF6JKha0RnNwNdzUeVGPr9Y8rdyNGP8OIPrB9wgRxYo8JmJSzflm AY8Xiwzcf62SfZK9NFSFB8mPgtR3hQBXn8vHX6/+/zcabWnmMvTylGem135+Krgpdwcn 1Z5Sqcp8Q7TmB1tW5/rE2/7eWjxguTwLijrN5pNdj+mIF3L4M5rhQqP/tQ5IimNKzlRT 4jXqmRzwGJzA1FE5yU26QSKvvYbtRamKfknW7yojpWrlJEGfwSzmD22le5+bqPn3fQiW wg== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 06/15] spapr: nested: Introduce H_GUEST_[GET|SET]_CAPABILITIES hcalls. Date: Thu, 18 Jan 2024 10:54:29 +0530 Message-Id: <20240118052438.1475437-7-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: RgIz3CVEb__8YunTLXYDca3TzNztUfaI X-Proofpoint-ORIG-GUID: M-qdFKtIDOw73_m5CGHirLAiboczIeYn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 mlxscore=0 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555651193100003 Content-Type: text/plain; charset="utf-8" Introduce the nested PAPR hcalls: - H_GUEST_GET_CAPABILITIES which is used to query the capabilities of the API and the L2 guests it provides. - H_GUEST_SET_CAPABILITIES which is used to set the Guest API capabilities that the Host Partition supports and may use. [amachhiw: support for p9 compat mode and return register bug fixes] Signed-off-by: Michael Neuling Signed-off-by: Amit Machhiwal Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr.h | 5 +- include/hw/ppc/spapr_nested.h | 13 +++++ hw/ppc/spapr_nested.c | 100 ++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 5521cbe5fb..5e0939fcc0 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -364,6 +364,7 @@ struct SpaprMachineState { #define H_NOOP -63 #define H_UNSUPPORTED -67 #define H_OVERLAP -68 +#define H_STATE -75 #define H_UNSUPPORTED_FLAG -256 #define H_MULTI_THREADS_ACTIVE -9005 =20 @@ -583,8 +584,10 @@ struct SpaprMachineState { #define H_RPT_INVALIDATE 0x448 #define H_SCM_FLUSH 0x44C #define H_WATCHDOG 0x45C +#define H_GUEST_GET_CAPABILITIES 0x460 +#define H_GUEST_SET_CAPABILITIES 0x464 =20 -#define MAX_HCALL_OPCODE H_WATCHDOG +#define MAX_HCALL_OPCODE H_GUEST_SET_CAPABILITIES =20 /* The hcalls above are standardized in PAPR and implemented by pHyp * as well. diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 28a102c273..ea617c4710 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -8,8 +8,20 @@ typedef struct SpaprMachineStateNested { uint64_t ptcr; uint8_t api; #define NESTED_API_KVM_HV 1 + bool capabilities_set; + uint32_t pvr_base; } SpaprMachineStateNested; =20 +/* Nested PAPR API related macros */ +#define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000 +#define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000 +#define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000 +#define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \ + H_GUEST_CAPABILITIES_P9_MODE) +#define H_GUEST_CAP_COPY_MEM_BMAP 0 +#define H_GUEST_CAP_P9_MODE_BMAP 1 +#define H_GUEST_CAP_P10_MODE_BMAP 2 + /* * Register state for entering a nested guest with H_ENTER_NESTED. * New member must be added at the end. @@ -108,4 +120,5 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr,= PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry); void spapr_nested_init(SpaprMachineState *spapr); uint8_t spapr_nested_api(SpaprMachineState *spapr); +void spapr_register_nested_papr(void); #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index afadd5b22d..d29224c3c9 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -7,10 +7,12 @@ #include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/spapr_nested.h" #include "mmu-book3s-v3.h" +#include "cpu-models.h" =20 void spapr_nested_init(SpaprMachineState *spapr) { spapr->nested.api =3D 0; + spapr->nested.capabilities_set =3D false; } =20 uint8_t spapr_nested_api(SpaprMachineState *spapr) @@ -426,6 +428,92 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) } } =20 +static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + + if (flags) { /* don't handle any flags capabilities for now */ + return H_PARAMETER; + } + + /* P10 capabilities */ + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, + spapr->max_compat_pvr)) { + env->gpr[4] |=3D H_GUEST_CAPABILITIES_P10_MODE; + } + + /* P9 capabilities */ + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, + spapr->max_compat_pvr)) { + env->gpr[4] |=3D H_GUEST_CAPABILITIES_P9_MODE; + } + + return H_SUCCESS; +} + +static target_ulong h_guest_set_capabilities(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + target_ulong capabilities =3D args[1]; + env->gpr[4] =3D 0; + + if (flags) { /* don't handle any flags capabilities for now */ + return H_PARAMETER; + } + + if (capabilities & H_GUEST_CAPABILITIES_COPY_MEM) { + env->gpr[4] =3D 1; + return H_P2; /* isn't supported */ + } + + /* If there are no capabilities configured, set the R5 to the index of + * the first supported Power Processor Mode + */ + if (!capabilities) { + env->gpr[4] =3D 1; + + /* set R5 to the first supported Power Processor Mode */ + if(ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0, + spapr->max_compat_pvr)) { + env->gpr[5] =3D H_GUEST_CAP_P10_MODE_BMAP; + } + else if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, + spapr->max_compat_pvr)) { + env->gpr[5] =3D H_GUEST_CAP_P9_MODE_BMAP; + } + + return H_P2; + } + + /* If an invalid capability is set, R5 should contain the index of the + * invalid capability bit + */ + if (capabilities & ~H_GUEST_CAP_VALID_MASK) { + env->gpr[4] =3D 1; + + /* Set R5 to the index of the invalid capability */ + env->gpr[5] =3D 63 - ctz64(capabilities); + + return H_P2; + } + + if (!spapr->nested.capabilities_set) { + spapr->nested.capabilities_set =3D true; + spapr->nested.pvr_base =3D env->spr[SPR_PVR]; + return H_SUCCESS; + } else { + return H_STATE; + } +} + void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); @@ -433,6 +521,13 @@ void spapr_register_nested_hv(void) spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate); spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_gue= st); } + +void spapr_register_nested_papr(void) +{ + spapr_register_hypercall(H_GUEST_GET_CAPABILITIES, h_guest_get_capabil= ities); + spapr_register_hypercall(H_GUEST_SET_CAPABILITIES, h_guest_set_capabil= ities); +} + #else void spapr_exit_nested(PowerPCCPU *cpu, int excp) { @@ -449,4 +544,9 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr,= PowerPCCPU *cpu, { return false; } + +void spapr_register_nested_papr(void) +{ + /* DO NOTHING */ +} #endif --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555709; cv=none; d=zohomail.com; s=zohoarc; b=O9kVb3sv8wzgAfQsTftdiKdQ+5ztnAjWzq9MuyUmSO5O9Oe3q5tfXyrI+1qP8PtbSMDV+5izVb82vUMChMzaBkb0hxOFszCY3qpHl3xvwF2u5F7iCcbtmMpbd+M3C6KgggoabNGaXlu3hnNt53hX7gNFeh1QLC9tNsJLHqCn5vU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555709; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 18 Jan 2024 05:25:04 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=JFqYtlh3ZnRchRdc4uetXL5jcE04VUHLPgTyGulm6+k=; b=op4KnvJdF3aieKE3f8NKXyRfIBf66JWCQWwTlB+Vxfhq2iyxq7gBrBKU3bLjg4AKjL2H PQf9LRiewtuX2asWn4rZ1CLY5Bhd9CXKyQfq/khA8qsxvRA6bKxq94Fj0PPobyZo+2iA hF+Y18Xuu5hVMWAtap2YaIb4XRJBwo006kqD2reVOTjlyNImzZMhIaWLLz8H7YZxwoDJ 61hzY+9r27d+f/tdhSoyVyM1o/Vn8sIcyPpzcZKiDGnFWT9TTNZ5QF0s22jR6CVphYx4 KBB5XU8WW6uNFiW1DoNEFg3dkk91+MYhzrjs1VMVX0NUhsWuS4C8G6un9speDEeF6Gzq hA== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 07/15] spapr: nested: Introduce H_GUEST_[CREATE|DELETE] hcalls. Date: Thu, 18 Jan 2024 10:54:30 +0530 Message-Id: <20240118052438.1475437-8-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: VMx4GiuXGeRQe7oQhD79uUn31oTXWqZg X-Proofpoint-ORIG-GUID: AL-R7Rervf_9nHwUzmyOhapoMqsb8CPq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=676 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555711463100003 Content-Type: text/plain; charset="utf-8" Introduce the nested PAPR hcalls: - H_GUEST_CREATE which is used to create and allocate resources for nested guest being created. - H_GUEST_DELETE which is used to delete and deallocate resources for the nested guest being deleted. It also supports deleting all nested guests at once using a deleteAll flag. [amachhiw: set capabilities check for no guests created before calling] Signed-off-by: Michael Neuling Signed-off-by: Amit Machhiwal Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr.h | 4 +- include/hw/ppc/spapr_nested.h | 7 +++ hw/ppc/spapr_nested.c | 106 ++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 5e0939fcc0..5a001a7c00 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -586,8 +586,10 @@ struct SpaprMachineState { #define H_WATCHDOG 0x45C #define H_GUEST_GET_CAPABILITIES 0x460 #define H_GUEST_SET_CAPABILITIES 0x464 +#define H_GUEST_CREATE 0x470 +#define H_GUEST_DELETE 0x488 =20 -#define MAX_HCALL_OPCODE H_GUEST_SET_CAPABILITIES +#define MAX_HCALL_OPCODE H_GUEST_DELETE =20 /* The hcalls above are standardized in PAPR and implemented by pHyp * as well. diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index ea617c4710..a01f8e37ab 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -10,8 +10,13 @@ typedef struct SpaprMachineStateNested { #define NESTED_API_KVM_HV 1 bool capabilities_set; uint32_t pvr_base; + GHashTable *guests; } SpaprMachineStateNested; =20 +typedef struct SpaprMachineStateNestedGuest { + uint32_t pvr_logical; +} SpaprMachineStateNestedGuest; + /* Nested PAPR API related macros */ #define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000 #define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000 @@ -21,6 +26,8 @@ typedef struct SpaprMachineStateNested { #define H_GUEST_CAP_COPY_MEM_BMAP 0 #define H_GUEST_CAP_P9_MODE_BMAP 1 #define H_GUEST_CAP_P10_MODE_BMAP 2 +#define PAPR_NESTED_GUEST_MAX 4096 +#define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL =20 /* * Register state for entering a nested guest with H_ENTER_NESTED. diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index d29224c3c9..1e620ef2fb 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -474,6 +474,11 @@ static target_ulong h_guest_set_capabilities(PowerPCCP= U *cpu, return H_P2; /* isn't supported */ } =20 + /* Confirm there are no guests created yet */ + if (spapr->nested.guests) { + return H_STATE; + } + /* If there are no capabilities configured, set the R5 to the index of * the first supported Power Processor Mode */ @@ -514,6 +519,105 @@ static target_ulong h_guest_set_capabilities(PowerPCC= PU *cpu, } } =20 +static void +destroy_guest_helper(gpointer value) +{ + struct SpaprMachineStateNestedGuest *guest =3D value; + g_free(guest); +} + +static target_ulong h_guest_create(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + target_ulong continue_token =3D args[1]; + uint64_t guestid; + int nguests =3D 0; + struct SpaprMachineStateNestedGuest *guest; + + if (flags) { /* don't handle any flags for now */ + return H_UNSUPPORTED_FLAG; + } + + if (continue_token !=3D -1) { + return H_P2; + } + + if (!spapr->nested.capabilities_set) { + return H_STATE; + } + + if (!spapr->nested.guests) { + spapr->nested.guests =3D g_hash_table_new_full(NULL, + NULL, + NULL, + destroy_guest_helper); + } + + nguests =3D g_hash_table_size(spapr->nested.guests); + + if (nguests =3D=3D PAPR_NESTED_GUEST_MAX) { + return H_NO_MEM; + } + + /* Lookup for available guestid */ + for (guestid =3D 1; guestid < PAPR_NESTED_GUEST_MAX; guestid++) { + if (!(g_hash_table_lookup(spapr->nested.guests, + GINT_TO_POINTER(guestid)))) { + break; + } + } + + if (guestid =3D=3D PAPR_NESTED_GUEST_MAX) { + return H_NO_MEM; + } + + guest =3D g_try_new0(struct SpaprMachineStateNestedGuest, 1); + if (!guest) { + return H_NO_MEM; + } + + guest->pvr_logical =3D spapr->nested.pvr_base; + g_hash_table_insert(spapr->nested.guests, GINT_TO_POINTER(guestid), gu= est); + env->gpr[4] =3D guestid; + + return H_SUCCESS; +} + +static target_ulong h_guest_delete(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + target_ulong flags =3D args[0]; + target_ulong guestid =3D args[1]; + struct SpaprMachineStateNestedGuest *guest; + + /* + * handle flag deleteAllGuests, if set: + * guestid is ignored and all guests are deleted + * + */ + if (flags & ~H_GUEST_DELETE_ALL_FLAG) { + return H_UNSUPPORTED_FLAG; /* other flag bits reserved */ + } else if (flags & H_GUEST_DELETE_ALL_FLAG) { + g_hash_table_destroy(spapr->nested.guests); + return H_SUCCESS; + } + + guest =3D g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(gu= estid)); + if (!guest) { + return H_P2; + } + + g_hash_table_remove(spapr->nested.guests, GINT_TO_POINTER(guestid)); + + return H_SUCCESS; +} + void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); @@ -526,6 +630,8 @@ void spapr_register_nested_papr(void) { spapr_register_hypercall(H_GUEST_GET_CAPABILITIES, h_guest_get_capabil= ities); spapr_register_hypercall(H_GUEST_SET_CAPABILITIES, h_guest_set_capabil= ities); + spapr_register_hypercall(H_GUEST_CREATE , h_guest_create); + spapr_register_hypercall(H_GUEST_DELETE , h_guest_delete); } =20 #else --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Date: Thu, 18 Jan 2024 10:54:31 +0530 Message-Id: <20240118052438.1475437-9-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: TXEM_mYIfzO8zRoz7XVpBMyB43W_xQkW X-Proofpoint-ORIG-GUID: U7kRLRYBz7als9ZqYnPCbXhpOVNtvaTB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=720 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555691283100001 Content-Type: text/plain; charset="utf-8" Introduce the nested PAPR hcall H_GUEST_CREATE_VCPU which is used to create and initialize the specified VCPU resource for the previously created guest. Each guest can have multiple VCPUs upto max 2048. All VCPUs for a guest gets deallocated on guest delete. Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr.h | 2 + include/hw/ppc/spapr_nested.h | 10 ++++ hw/ppc/spapr_nested.c | 96 +++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 5a001a7c00..fb5e8c093d 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -365,6 +365,7 @@ struct SpaprMachineState { #define H_UNSUPPORTED -67 #define H_OVERLAP -68 #define H_STATE -75 +#define H_IN_USE -77 #define H_UNSUPPORTED_FLAG -256 #define H_MULTI_THREADS_ACTIVE -9005 =20 @@ -587,6 +588,7 @@ struct SpaprMachineState { #define H_GUEST_GET_CAPABILITIES 0x460 #define H_GUEST_SET_CAPABILITIES 0x464 #define H_GUEST_CREATE 0x470 +#define H_GUEST_CREATE_VCPU 0x474 #define H_GUEST_DELETE 0x488 =20 #define MAX_HCALL_OPCODE H_GUEST_DELETE diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index a01f8e37ab..4a9a13089d 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -15,6 +15,8 @@ typedef struct SpaprMachineStateNested { =20 typedef struct SpaprMachineStateNestedGuest { uint32_t pvr_logical; + unsigned long vcpus; + struct SpaprMachineStateNestedGuestVcpu *vcpu; } SpaprMachineStateNestedGuest; =20 /* Nested PAPR API related macros */ @@ -28,6 +30,7 @@ typedef struct SpaprMachineStateNestedGuest { #define H_GUEST_CAP_P10_MODE_BMAP 2 #define PAPR_NESTED_GUEST_MAX 4096 #define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL +#define PAPR_NESTED_GUEST_VCPU_MAX 2048 =20 /* * Register state for entering a nested guest with H_ENTER_NESTED. @@ -119,8 +122,15 @@ struct nested_ppc_state { uint64_t ppr; =20 int64_t tb_offset; + /* Nested PAPR API */ + uint64_t pvr; }; =20 +typedef struct SpaprMachineStateNestedGuestVcpu { + bool enabled; + struct nested_ppc_state state; +} SpaprMachineStateNestedGuestVcpu; + void spapr_exit_nested(PowerPCCPU *cpu, int excp); typedef struct SpaprMachineState SpaprMachineState; bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 1e620ef2fb..127f3facd2 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -428,6 +428,41 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) } } =20 +static +SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *sp= apr, + target_ulong guestid) +{ + SpaprMachineStateNestedGuest *guest; + + guest =3D g_hash_table_lookup(spapr->nested.guests, GINT_TO_POINTER(gu= estid)); + return guest; +} + +static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest, + target_ulong vcpuid) +{ + struct SpaprMachineStateNestedGuestVcpu *vcpu; + /* + * Perform sanity checks for the provided vcpuid of a guest. + * For now, ensure its valid, allocated and enabled for use. + */ + + if (vcpuid >=3D PAPR_NESTED_GUEST_VCPU_MAX) { + return false; + } + + if (!(vcpuid < guest->vcpus)) { + return false; + } + + vcpu =3D &guest->vcpu[vcpuid]; + if (!vcpu->enabled) { + return false; + } + + return true; +} + static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong opcode, @@ -523,6 +558,7 @@ static void destroy_guest_helper(gpointer value) { struct SpaprMachineStateNestedGuest *guest =3D value; + g_free(guest->vcpu); g_free(guest); } =20 @@ -618,6 +654,65 @@ static target_ulong h_guest_delete(PowerPCCPU *cpu, return H_SUCCESS; } =20 +static target_ulong h_guest_create_vcpu(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + struct nested_ppc_state *l2_state; + target_ulong flags =3D args[0]; + target_ulong guestid =3D args[1]; + target_ulong vcpuid =3D args[2]; + SpaprMachineStateNestedGuest *guest; + + if (flags) { /* don't handle any flags for now */ + return H_UNSUPPORTED_FLAG; + } + + guest =3D spapr_get_nested_guest(spapr, guestid); + if (!guest) { + return H_P2; + } + + if (vcpuid < guest->vcpus) { + return H_IN_USE; + } + + if (guest->vcpus >=3D PAPR_NESTED_GUEST_VCPU_MAX) { + return H_P3; + } + + if (guest->vcpus) { + SpaprMachineStateNestedGuestVcpu *vcpus; + vcpus =3D g_try_renew(struct SpaprMachineStateNestedGuestVcpu, + guest->vcpu, + guest->vcpus + 1); + if (!vcpus) { + return H_NO_MEM; + } + memset(&vcpus[guest->vcpus], 0, + sizeof(SpaprMachineStateNestedGuestVcpu)); + guest->vcpu =3D vcpus; + } else { + guest->vcpu =3D g_try_new0(SpaprMachineStateNestedGuestVcpu, 1); + if (guest->vcpu =3D=3D NULL) { + return H_NO_MEM; + } + } + l2_state =3D &guest->vcpu[guest->vcpus].state; + guest->vcpus++; + assert(vcpuid < guest->vcpus); /* linear vcpuid allocation only */ + /* Set L1 PVR as L2 default */ + l2_state->pvr =3D env->spr[SPR_PVR]; + guest->vcpu[vcpuid].enabled =3D true; + + if (!spapr_nested_vcpu_check(guest, vcpuid)) { + return H_PARAMETER; + } + return H_SUCCESS; +} + void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); @@ -632,6 +727,7 @@ void spapr_register_nested_papr(void) spapr_register_hypercall(H_GUEST_SET_CAPABILITIES, h_guest_set_capabil= ities); spapr_register_hypercall(H_GUEST_CREATE , h_guest_create); spapr_register_hypercall(H_GUEST_DELETE , h_guest_delete); + spapr_register_hypercall(H_GUEST_CREATE_VCPU , h_guest_create_vcpu= ); } =20 #else --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 18 Jan 2024 05:25:10 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D7F722004B; Thu, 18 Jan 2024 05:25:09 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4322A20040; Thu, 18 Jan 2024 05:25:08 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.in.ibm.com (unknown [9.109.243.35]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 Jan 2024 05:25:08 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=kcM0SeI1NC+wkvqIrnPQEjZvRCWVbOfww7LEu2R9fGE=; b=Zm+AaHg1p2FX3bYb/Gw9uZP7dB2oCBakDOvW7vfyc1wiepBKs6b2XNBrT8+HyN1h9/l6 c0h2P8RxifJtQBl22FAGp/XJszXVwJ6Iiu8jj8QbegPJJpIKDYZYEwAfyZ3VxREomxoB auooyTS2OKFEAOqf1wv95IZPmhAOG2MpiZQvPAUUdi/E7FVN2D4QxKf4K3j7g5nDtSuR pDvrNByRYPm6bJ7LmPYwfLLZzqB+lMkafEMRB/9o5t+q1f2Tvg1QaE1Y3Jm9COnjlWY9 URHoOeaalBg14weSiX2B0YMyaZMFJzhL61sFMnNVHxuCPuLPZQZOSUAvu3iPz5rXFwxg Xg== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 09/15] spapr: nested: Extend nested_ppc_state for nested PAPR API Date: Thu, 18 Jan 2024 10:54:32 +0530 Message-Id: <20240118052438.1475437-10-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: H89nRlXJgpkNEGZ1rQqC7nTvB-Bf26Sv X-Proofpoint-ORIG-GUID: XO8-q8Oxk0abqHH-JDBw5h9pBlwyQ7Nj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=804 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555645130100003 Content-Type: text/plain; charset="utf-8" Currently, nested_ppc_state stores a certain set of registers and works with nested_[load|save]_state() for state transfer as reqd for nested-hv AP= I. Extending these with additional registers state as reqd for nested PAPR API. Signed-off-by: Harsh Prateek Bora Suggested-by: Nicholas Piggin --- include/hw/ppc/spapr_nested.h | 49 ++++++++++++++++ target/ppc/cpu.h | 2 + hw/ppc/spapr_nested.c | 106 ++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 4a9a13089d..42f1bdb2e5 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -8,6 +8,7 @@ typedef struct SpaprMachineStateNested { uint64_t ptcr; uint8_t api; #define NESTED_API_KVM_HV 1 +#define NESTED_API_PAPR 2 bool capabilities_set; uint32_t pvr_base; GHashTable *guests; @@ -124,6 +125,54 @@ struct nested_ppc_state { int64_t tb_offset; /* Nested PAPR API */ uint64_t pvr; + uint64_t amor; + uint64_t dawr0; + uint64_t dawrx0; + uint64_t ciabr; + uint64_t purr; + uint64_t spurr; + uint64_t ic; + uint64_t vtb; + uint64_t hdar; + uint64_t hdsisr; + uint64_t heir; + uint64_t asdr; + uint64_t dawr1; + uint64_t dawrx1; + uint64_t dexcr; + uint64_t hdexcr; + uint64_t hashkeyr; + uint64_t hashpkeyr; + ppc_vsr_t vsr[64] QEMU_ALIGNED(16); + uint64_t ebbhr; + uint64_t tar; + uint64_t ebbrr; + uint64_t bescr; + uint64_t iamr; + uint64_t amr; + uint64_t uamor; + uint64_t dscr; + uint64_t fscr; + uint64_t pspb; + uint64_t ctrl; + uint64_t vrsave; + uint64_t dar; + uint64_t dsisr; + uint64_t pmc1; + uint64_t pmc2; + uint64_t pmc3; + uint64_t pmc4; + uint64_t pmc5; + uint64_t pmc6; + uint64_t mmcr0; + uint64_t mmcr1; + uint64_t mmcr2; + uint64_t mmcra; + uint64_t sdar; + uint64_t siar; + uint64_t sier; + uint32_t vscr; + uint64_t fpscr; }; =20 typedef struct SpaprMachineStateNestedGuestVcpu { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..dd680178d8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1737,9 +1737,11 @@ void ppc_compat_add_property(Object *obj, const char= *name, #define SPR_PSPB (0x09F) #define SPR_DPDES (0x0B0) #define SPR_DAWR0 (0x0B4) +#define SPR_DAWR1 (0x0B5) #define SPR_RPR (0x0BA) #define SPR_CIABR (0x0BB) #define SPR_DAWRX0 (0x0BC) +#define SPR_DAWRX1 (0x0BD) #define SPR_HFSCR (0x0BE) #define SPR_VRSAVE (0x100) #define SPR_USPRG0 (0x100) diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 127f3facd2..e329afb466 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -101,6 +101,7 @@ static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *c= pu) { CPUPPCState *env =3D &cpu->env; + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); =20 memcpy(save->gpr, env->gpr, sizeof(save->gpr)); =20 @@ -127,6 +128,58 @@ static void nested_save_state(struct nested_ppc_state = *save, PowerPCCPU *cpu) save->pidr =3D env->spr[SPR_BOOKS_PID]; save->ppr =3D env->spr[SPR_PPR]; =20 + if (spapr_nested_api(spapr) =3D=3D NESTED_API_PAPR) { + save->pvr =3D env->spr[SPR_PVR]; + save->amor =3D env->spr[SPR_AMOR]; + save->dawr0 =3D env->spr[SPR_DAWR0]; + save->dawrx0 =3D env->spr[SPR_DAWRX0]; + save->ciabr =3D env->spr[SPR_CIABR]; + save->purr =3D env->spr[SPR_PURR]; + save->spurr =3D env->spr[SPR_SPURR]; + save->ic =3D env->spr[SPR_IC]; + save->vtb =3D env->spr[SPR_VTB]; + save->hdar =3D env->spr[SPR_HDAR]; + save->hdsisr =3D env->spr[SPR_HDSISR]; + save->heir =3D env->spr[SPR_HEIR]; + save->asdr =3D env->spr[SPR_ASDR]; + save->dawr1 =3D env->spr[SPR_DAWR1]; + save->dawrx1 =3D env->spr[SPR_DAWRX1]; + save->dexcr =3D env->spr[SPR_DEXCR]; + save->hdexcr =3D env->spr[SPR_HDEXCR]; + save->hashkeyr =3D env->spr[SPR_HASHKEYR]; + save->hashpkeyr =3D env->spr[SPR_HASHPKEYR]; + memcpy(save->vsr, env->vsr, sizeof(save->vsr)); + save->ebbhr =3D env->spr[SPR_EBBHR]; + save->tar =3D env->spr[SPR_TAR]; + save->ebbrr =3D env->spr[SPR_EBBRR]; + save->bescr =3D env->spr[SPR_BESCR]; + save->iamr =3D env->spr[SPR_IAMR]; + save->amr =3D env->spr[SPR_AMR]; + save->uamor =3D env->spr[SPR_UAMOR]; + save->dscr =3D env->spr[SPR_DSCR]; + save->fscr =3D env->spr[SPR_FSCR]; + save->pspb =3D env->spr[SPR_PSPB]; + save->ctrl =3D env->spr[SPR_CTRL]; + save->vrsave =3D env->spr[SPR_VRSAVE]; + save->dar =3D env->spr[SPR_DAR]; + save->dsisr =3D env->spr[SPR_DSISR]; + save->pmc1 =3D env->spr[SPR_POWER_PMC1]; + save->pmc2 =3D env->spr[SPR_POWER_PMC2]; + save->pmc3 =3D env->spr[SPR_POWER_PMC3]; + save->pmc4 =3D env->spr[SPR_POWER_PMC4]; + save->pmc5 =3D env->spr[SPR_POWER_PMC5]; + save->pmc6 =3D env->spr[SPR_POWER_PMC6]; + save->mmcr0 =3D env->spr[SPR_POWER_MMCR0]; + save->mmcr1 =3D env->spr[SPR_POWER_MMCR1]; + save->mmcr2 =3D env->spr[SPR_POWER_MMCR2]; + save->mmcra =3D env->spr[SPR_POWER_MMCRA]; + save->sdar =3D env->spr[SPR_POWER_SDAR]; + save->siar =3D env->spr[SPR_POWER_SIAR]; + save->sier =3D env->spr[SPR_POWER_SIER]; + save->vscr =3D ppc_get_vscr(env); + save->fpscr =3D env->fpscr; + } + save->tb_offset =3D env->tb_env->tb_offset; } =20 @@ -134,6 +187,7 @@ static void nested_load_state(PowerPCCPU *cpu, struct n= ested_ppc_state *load) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); =20 memcpy(env->gpr, load->gpr, sizeof(env->gpr)); =20 @@ -160,6 +214,58 @@ static void nested_load_state(PowerPCCPU *cpu, struct = nested_ppc_state *load) env->spr[SPR_BOOKS_PID] =3D load->pidr; env->spr[SPR_PPR] =3D load->ppr; =20 + if (spapr_nested_api(spapr) =3D=3D NESTED_API_PAPR) { + env->spr[SPR_PVR] =3D load->pvr; + env->spr[SPR_AMOR] =3D load->amor; + env->spr[SPR_DAWR0] =3D load->dawr0; + env->spr[SPR_DAWRX0] =3D load->dawrx0; + env->spr[SPR_CIABR] =3D load->ciabr; + env->spr[SPR_PURR] =3D load->purr; + env->spr[SPR_SPURR] =3D load->purr; + env->spr[SPR_IC] =3D load->ic; + env->spr[SPR_VTB] =3D load->vtb; + env->spr[SPR_HDAR] =3D load->hdar; + env->spr[SPR_HDSISR] =3D load->hdsisr; + env->spr[SPR_HEIR] =3D load->heir; + env->spr[SPR_ASDR] =3D load->asdr; + env->spr[SPR_DAWR1] =3D load->dawr1; + env->spr[SPR_DAWRX1] =3D load->dawrx1; + env->spr[SPR_DEXCR] =3D load->dexcr; + env->spr[SPR_HDEXCR] =3D load->hdexcr; + env->spr[SPR_HASHKEYR] =3D load->hashkeyr; + env->spr[SPR_HASHPKEYR] =3D load->hashpkeyr; + memcpy(env->vsr, load->vsr, sizeof(env->vsr)); + env->spr[SPR_EBBHR] =3D load->ebbhr; + env->spr[SPR_TAR] =3D load->tar; + env->spr[SPR_EBBRR] =3D load->ebbrr; + env->spr[SPR_BESCR] =3D load->bescr; + env->spr[SPR_IAMR] =3D load->iamr; + env->spr[SPR_AMR] =3D load->amr; + env->spr[SPR_UAMOR] =3D load->uamor; + env->spr[SPR_DSCR] =3D load->dscr; + env->spr[SPR_FSCR] =3D load->fscr; + env->spr[SPR_PSPB] =3D load->pspb; + env->spr[SPR_CTRL] =3D load->ctrl; + env->spr[SPR_VRSAVE] =3D load->vrsave; + env->spr[SPR_DAR] =3D load->dar; + env->spr[SPR_DSISR] =3D load->dsisr; + env->spr[SPR_POWER_PMC1] =3D load->pmc1; + env->spr[SPR_POWER_PMC2] =3D load->pmc2; + env->spr[SPR_POWER_PMC3] =3D load->pmc3; + env->spr[SPR_POWER_PMC4] =3D load->pmc4; + env->spr[SPR_POWER_PMC5] =3D load->pmc5; + env->spr[SPR_POWER_PMC6] =3D load->pmc6; + env->spr[SPR_POWER_MMCR0] =3D load->mmcr0; + env->spr[SPR_POWER_MMCR1] =3D load->mmcr1; + env->spr[SPR_POWER_MMCR2] =3D load->mmcr2; + env->spr[SPR_POWER_MMCRA] =3D load->mmcra; + env->spr[SPR_POWER_SDAR] =3D load->sdar; + env->spr[SPR_POWER_SIAR] =3D load->siar; + env->spr[SPR_POWER_SIER] =3D load->sier; + ppc_store_vscr(env, load->vscr); + ppc_store_fpscr(env, load->fpscr); + } + env->tb_env->tb_offset =3D load->tb_offset; =20 /* --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Date: Thu, 18 Jan 2024 10:54:33 +0530 Message-Id: <20240118052438.1475437-11-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: UfPUlnpzfgnMy5aIcUmnrX4L1CrWRpT5 X-Proofpoint-GUID: s05089bPBTlp24CEtahMcqiezGdB6osC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 spamscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555733527100003 Content-Type: text/plain; charset="utf-8" Nested PAPR API provides a standard Guest State Buffer (GSB) format with unique IDs for each guest state element for which get/set state is supported by the API. Some of the elements are read-only and/or guest-wide. Introducing helper routines for state exchange of each of the nested guest state elements for which get/set state should be supported by the API. Signed-off-by: Michael Neuling Signed-off-by: Shivaprasad G Bhat Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr_nested.h | 303 +++++++++++++++++++++++ hw/ppc/spapr_nested.c | 442 +++++++++++++++++++++++++++++++++- 2 files changed, 742 insertions(+), 3 deletions(-) diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 42f1bdb2e5..a71aa3fada 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -4,6 +4,191 @@ #include "qemu/osdep.h" #include "target/ppc/cpu.h" =20 +/* Guest State Buffer Element IDs */ +#define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignore= d */ +#define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state si= ze */ +#define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buf= fer */ +#define GSB_VCPU_LPVR 0x0003 /* Logical PVR */ +#define GSB_TB_OFFSET 0x0004 /* Timebase Offset */ +#define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */ +#define GSB_PROCESS_TBL 0x0006 /* Process Table */ + /* RESERVED 0x0007 - 0x0BFF */ +#define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */ +#define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */ +#define GSB_VCPU_VPA 0x0C02 /* HRA to Guest VCPU VPA */ + /* RESERVED 0x0C03 - 0x0FFF */ +#define GSB_VCPU_GPR0 0x1000 +#define GSB_VCPU_GPR1 0x1001 +#define GSB_VCPU_GPR2 0x1002 +#define GSB_VCPU_GPR3 0x1003 +#define GSB_VCPU_GPR4 0x1004 +#define GSB_VCPU_GPR5 0x1005 +#define GSB_VCPU_GPR6 0x1006 +#define GSB_VCPU_GPR7 0x1007 +#define GSB_VCPU_GPR8 0x1008 +#define GSB_VCPU_GPR9 0x1009 +#define GSB_VCPU_GPR10 0x100A +#define GSB_VCPU_GPR11 0x100B +#define GSB_VCPU_GPR12 0x100C +#define GSB_VCPU_GPR13 0x100D +#define GSB_VCPU_GPR14 0x100E +#define GSB_VCPU_GPR15 0x100F +#define GSB_VCPU_GPR16 0x1010 +#define GSB_VCPU_GPR17 0x1011 +#define GSB_VCPU_GPR18 0x1012 +#define GSB_VCPU_GPR19 0x1013 +#define GSB_VCPU_GPR20 0x1014 +#define GSB_VCPU_GPR21 0x1015 +#define GSB_VCPU_GPR22 0x1016 +#define GSB_VCPU_GPR23 0x1017 +#define GSB_VCPU_GPR24 0x1018 +#define GSB_VCPU_GPR25 0x1019 +#define GSB_VCPU_GPR26 0x101A +#define GSB_VCPU_GPR27 0x101B +#define GSB_VCPU_GPR28 0x101C +#define GSB_VCPU_GPR29 0x101D +#define GSB_VCPU_GPR30 0x101E +#define GSB_VCPU_GPR31 0x101F +#define GSB_VCPU_HDEC_EXPIRY_TB 0x1020 +#define GSB_VCPU_SPR_NIA 0x1021 +#define GSB_VCPU_SPR_MSR 0x1022 +#define GSB_VCPU_SPR_LR 0x1023 +#define GSB_VCPU_SPR_XER 0x1024 +#define GSB_VCPU_SPR_CTR 0x1025 +#define GSB_VCPU_SPR_CFAR 0x1026 +#define GSB_VCPU_SPR_SRR0 0x1027 +#define GSB_VCPU_SPR_SRR1 0x1028 +#define GSB_VCPU_SPR_DAR 0x1029 +#define GSB_VCPU_DEC_EXPIRE_TB 0x102A +#define GSB_VCPU_SPR_VTB 0x102B +#define GSB_VCPU_SPR_LPCR 0x102C +#define GSB_VCPU_SPR_HFSCR 0x102D +#define GSB_VCPU_SPR_FSCR 0x102E +#define GSB_VCPU_SPR_FPSCR 0x102F +#define GSB_VCPU_SPR_DAWR0 0x1030 +#define GSB_VCPU_SPR_DAWR1 0x1031 +#define GSB_VCPU_SPR_CIABR 0x1032 +#define GSB_VCPU_SPR_PURR 0x1033 +#define GSB_VCPU_SPR_SPURR 0x1034 +#define GSB_VCPU_SPR_IC 0x1035 +#define GSB_VCPU_SPR_SPRG0 0x1036 +#define GSB_VCPU_SPR_SPRG1 0x1037 +#define GSB_VCPU_SPR_SPRG2 0x1038 +#define GSB_VCPU_SPR_SPRG3 0x1039 +#define GSB_VCPU_SPR_PPR 0x103A +#define GSB_VCPU_SPR_MMCR0 0x103B +#define GSB_VCPU_SPR_MMCR1 0x103C +#define GSB_VCPU_SPR_MMCR2 0x103D +#define GSB_VCPU_SPR_MMCR3 0x103E +#define GSB_VCPU_SPR_MMCRA 0x103F +#define GSB_VCPU_SPR_SIER 0x1040 +#define GSB_VCPU_SPR_SIER2 0x1041 +#define GSB_VCPU_SPR_SIER3 0x1042 +#define GSB_VCPU_SPR_BESCR 0x1043 +#define GSB_VCPU_SPR_EBBHR 0x1044 +#define GSB_VCPU_SPR_EBBRR 0x1045 +#define GSB_VCPU_SPR_AMR 0x1046 +#define GSB_VCPU_SPR_IAMR 0x1047 +#define GSB_VCPU_SPR_AMOR 0x1048 +#define GSB_VCPU_SPR_UAMOR 0x1049 +#define GSB_VCPU_SPR_SDAR 0x104A +#define GSB_VCPU_SPR_SIAR 0x104B +#define GSB_VCPU_SPR_DSCR 0x104C +#define GSB_VCPU_SPR_TAR 0x104D +#define GSB_VCPU_SPR_DEXCR 0x104E +#define GSB_VCPU_SPR_HDEXCR 0x104F +#define GSB_VCPU_SPR_HASHKEYR 0x1050 +#define GSB_VCPU_SPR_HASHPKEYR 0x1051 +#define GSB_VCPU_SPR_CTRL 0x1052 + /* RESERVED 0x1053 - 0x1FFF */ +#define GSB_VCPU_SPR_CR 0x2000 +#define GSB_VCPU_SPR_PIDR 0x2001 +#define GSB_VCPU_SPR_DSISR 0x2002 +#define GSB_VCPU_SPR_VSCR 0x2003 +#define GSB_VCPU_SPR_VRSAVE 0x2004 +#define GSB_VCPU_SPR_DAWRX0 0x2005 +#define GSB_VCPU_SPR_DAWRX1 0x2006 +#define GSB_VCPU_SPR_PMC1 0x2007 +#define GSB_VCPU_SPR_PMC2 0x2008 +#define GSB_VCPU_SPR_PMC3 0x2009 +#define GSB_VCPU_SPR_PMC4 0x200A +#define GSB_VCPU_SPR_PMC5 0x200B +#define GSB_VCPU_SPR_PMC6 0x200C +#define GSB_VCPU_SPR_WORT 0x200D +#define GSB_VCPU_SPR_PSPB 0x200E + /* RESERVED 0x200F - 0x2FFF */ +#define GSB_VCPU_SPR_VSR0 0x3000 +#define GSB_VCPU_SPR_VSR1 0x3001 +#define GSB_VCPU_SPR_VSR2 0x3002 +#define GSB_VCPU_SPR_VSR3 0x3003 +#define GSB_VCPU_SPR_VSR4 0x3004 +#define GSB_VCPU_SPR_VSR5 0x3005 +#define GSB_VCPU_SPR_VSR6 0x3006 +#define GSB_VCPU_SPR_VSR7 0x3007 +#define GSB_VCPU_SPR_VSR8 0x3008 +#define GSB_VCPU_SPR_VSR9 0x3009 +#define GSB_VCPU_SPR_VSR10 0x300A +#define GSB_VCPU_SPR_VSR11 0x300B +#define GSB_VCPU_SPR_VSR12 0x300C +#define GSB_VCPU_SPR_VSR13 0x300D +#define GSB_VCPU_SPR_VSR14 0x300E +#define GSB_VCPU_SPR_VSR15 0x300F +#define GSB_VCPU_SPR_VSR16 0x3010 +#define GSB_VCPU_SPR_VSR17 0x3011 +#define GSB_VCPU_SPR_VSR18 0x3012 +#define GSB_VCPU_SPR_VSR19 0x3013 +#define GSB_VCPU_SPR_VSR20 0x3014 +#define GSB_VCPU_SPR_VSR21 0x3015 +#define GSB_VCPU_SPR_VSR22 0x3016 +#define GSB_VCPU_SPR_VSR23 0x3017 +#define GSB_VCPU_SPR_VSR24 0x3018 +#define GSB_VCPU_SPR_VSR25 0x3019 +#define GSB_VCPU_SPR_VSR26 0x301A +#define GSB_VCPU_SPR_VSR27 0x301B +#define GSB_VCPU_SPR_VSR28 0x301C +#define GSB_VCPU_SPR_VSR29 0x301D +#define GSB_VCPU_SPR_VSR30 0x301E +#define GSB_VCPU_SPR_VSR31 0x301F +#define GSB_VCPU_SPR_VSR32 0x3020 +#define GSB_VCPU_SPR_VSR33 0x3021 +#define GSB_VCPU_SPR_VSR34 0x3022 +#define GSB_VCPU_SPR_VSR35 0x3023 +#define GSB_VCPU_SPR_VSR36 0x3024 +#define GSB_VCPU_SPR_VSR37 0x3025 +#define GSB_VCPU_SPR_VSR38 0x3026 +#define GSB_VCPU_SPR_VSR39 0x3027 +#define GSB_VCPU_SPR_VSR40 0x3028 +#define GSB_VCPU_SPR_VSR41 0x3029 +#define GSB_VCPU_SPR_VSR42 0x302A +#define GSB_VCPU_SPR_VSR43 0x302B +#define GSB_VCPU_SPR_VSR44 0x302C +#define GSB_VCPU_SPR_VSR45 0x302D +#define GSB_VCPU_SPR_VSR46 0x302E +#define GSB_VCPU_SPR_VSR47 0x302F +#define GSB_VCPU_SPR_VSR48 0x3030 +#define GSB_VCPU_SPR_VSR49 0x3031 +#define GSB_VCPU_SPR_VSR50 0x3032 +#define GSB_VCPU_SPR_VSR51 0x3033 +#define GSB_VCPU_SPR_VSR52 0x3034 +#define GSB_VCPU_SPR_VSR53 0x3035 +#define GSB_VCPU_SPR_VSR54 0x3036 +#define GSB_VCPU_SPR_VSR55 0x3037 +#define GSB_VCPU_SPR_VSR56 0x3038 +#define GSB_VCPU_SPR_VSR57 0x3039 +#define GSB_VCPU_SPR_VSR58 0x303A +#define GSB_VCPU_SPR_VSR59 0x303B +#define GSB_VCPU_SPR_VSR60 0x303C +#define GSB_VCPU_SPR_VSR61 0x303D +#define GSB_VCPU_SPR_VSR62 0x303E +#define GSB_VCPU_SPR_VSR63 0x303F + /* RESERVED 0x3040 - 0xEFFF */ +#define GSB_VCPU_SPR_HDAR 0xF000 +#define GSB_VCPU_SPR_HDSISR 0xF001 +#define GSB_VCPU_SPR_HEIR 0xF002 +#define GSB_VCPU_SPR_ASDR 0xF003 +/* End of list of Guest State Buffer Element IDs */ +#define GSB_LAST GSB_VCPU_SPR_ASDR + typedef struct SpaprMachineStateNested { uint64_t ptcr; uint8_t api; @@ -17,6 +202,8 @@ typedef struct SpaprMachineStateNested { typedef struct SpaprMachineStateNestedGuest { uint32_t pvr_logical; unsigned long vcpus; + uint64_t parttbl[2]; + uint64_t tb_offset; struct SpaprMachineStateNestedGuestVcpu *vcpu; } SpaprMachineStateNestedGuest; =20 @@ -32,6 +219,99 @@ typedef struct SpaprMachineStateNestedGuest { #define PAPR_NESTED_GUEST_MAX 4096 #define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL #define PAPR_NESTED_GUEST_VCPU_MAX 2048 +#define VCPU_OUT_BUF_MIN_SZ 0x80ULL +#define HVMASK_DEFAULT 0xffffffffffffffff +#define HVMASK_LPCR 0x0070000003820800 +#define HVMASK_MSR 0xEBFFFFFFFFBFEFFF +#define HVMASK_HDEXCR 0x00000000FFFFFFFF +#define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF + +#define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \ + .id =3D (i), \ + .size =3D (sz), \ + .location =3D ptr, \ + .offset =3D offsetof(struct s, f), \ + .copy =3D (c) \ +} + +#define GSBE_NESTED(i, sz, f, c) { \ + .id =3D (i), \ + .size =3D (sz), \ + .location =3D get_guest_ptr, \ + .offset =3D offsetof(struct SpaprMachineStateNestedGuest, f),\ + .copy =3D (c), \ + .mask =3D HVMASK_DEFAULT \ +} + +#define GSBE_NESTED_MSK(i, sz, f, c, m) { \ + .id =3D (i), \ + .size =3D (sz), \ + .location =3D get_guest_ptr, \ + .offset =3D offsetof(struct SpaprMachineStateNestedGuest, f),\ + .copy =3D (c), \ + .mask =3D (m) \ +} + +#define GSBE_NESTED_VCPU(i, sz, f, c) { \ + .id =3D (i), \ + .size =3D (sz), \ + .location =3D get_vcpu_ptr, \ + .offset =3D offsetof(struct SpaprMachineStateNestedGuestVcpu, f),\ + .copy =3D (c), \ + .mask =3D HVMASK_DEFAULT \ +} + +#define GUEST_STATE_ELEMENT_NOP(i, sz) { \ + .id =3D (i), \ + .size =3D (sz), \ + .location =3D NULL, \ + .offset =3D 0, \ + .copy =3D NULL, \ + .mask =3D HVMASK_DEFAULT \ +} + +#define GUEST_STATE_ELEMENT_NOP_DW(i) \ + GUEST_STATE_ELEMENT_NOP(i, 8) +#define GUEST_STATE_ELEMENT_NOP_W(i) \ + GUEST_STATE_ELEMENT_NOP(i, 4) + +#define GUEST_STATE_ELEMENT_BASE(i, s, c) { \ + .id =3D (i), \ + .size =3D (s), \ + .location =3D get_vcpu_state_ptr, \ + .offset =3D 0, \ + .copy =3D (c), \ + .mask =3D HVMASK_DEFAULT \ + } + +#define GUEST_STATE_ELEMENT_OFF(i, s, f, c) { \ + .id =3D (i), \ + .size =3D (s), \ + .location =3D get_vcpu_state_ptr, \ + .offset =3D offsetof(struct nested_ppc_state, f), \ + .copy =3D (c), \ + .mask =3D HVMASK_DEFAULT \ + } + +#define GUEST_STATE_ELEMENT_MSK(i, s, f, c, m) { \ + .id =3D (i), \ + .size =3D (s), \ + .location =3D get_vcpu_state_ptr, \ + .offset =3D offsetof(struct nested_ppc_state, f), \ + .copy =3D (c), \ + .mask =3D (m) \ + } + +#define GUEST_STATE_ELEMENT_ENV_QW(i, f) \ + GUEST_STATE_ELEMENT_OFF(i, 16, f, copy_state_16to16) +#define GUEST_STATE_ELEMENT_ENV_DW(i, f) \ + GUEST_STATE_ELEMENT_OFF(i, 8, f, copy_state_8to8) +#define GUEST_STATE_ELEMENT_ENV_W(i, f) \ + GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to8) +#define GUEST_STATE_ELEMENT_ENV_WW(i, f) \ + GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to4) +#define GSE_ENV_DWM(i, f, m) \ + GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m) =20 /* * Register state for entering a nested guest with H_ENTER_NESTED. @@ -173,13 +453,35 @@ struct nested_ppc_state { uint64_t sier; uint32_t vscr; uint64_t fpscr; + int64_t dec_expiry_tb; +}; + +struct SpaprMachineStateNestedGuestVcpuRunBuf { + uint64_t addr; + uint64_t size; }; =20 typedef struct SpaprMachineStateNestedGuestVcpu { bool enabled; struct nested_ppc_state state; + struct SpaprMachineStateNestedGuestVcpuRunBuf runbufin; + struct SpaprMachineStateNestedGuestVcpuRunBuf runbufout; + int64_t tb_offset; + uint64_t hdecr_expiry_tb; } SpaprMachineStateNestedGuestVcpu; =20 +struct guest_state_element_type { + uint16_t id; + int size; +#define GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE 0x1 +#define GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY 0x2 + uint16_t flags; + void *(*location)(SpaprMachineStateNestedGuest *, target_ulong); + size_t offset; + void (*copy)(void *, void *, bool); + uint64_t mask; +}; + void spapr_exit_nested(PowerPCCPU *cpu, int excp); typedef struct SpaprMachineState SpaprMachineState; bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, @@ -187,4 +489,5 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr,= PowerPCCPU *cpu, void spapr_nested_init(SpaprMachineState *spapr); uint8_t spapr_nested_api(SpaprMachineState *spapr); void spapr_register_nested_papr(void); +void spapr_nested_gsb_init(void); #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index e329afb466..4e8b392144 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -13,6 +13,7 @@ void spapr_nested_init(SpaprMachineState *spapr) { spapr->nested.api =3D 0; spapr->nested.capabilities_set =3D false; + spapr_nested_gsb_init(); } =20 uint8_t spapr_nested_api(SpaprMachineState *spapr) @@ -545,7 +546,7 @@ SpaprMachineStateNestedGuest *spapr_get_nested_guest(Sp= aprMachineState *spapr, } =20 static bool spapr_nested_vcpu_check(SpaprMachineStateNestedGuest *guest, - target_ulong vcpuid) + target_ulong vcpuid, bool inoutbuf) { struct SpaprMachineStateNestedGuestVcpu *vcpu; /* @@ -566,7 +567,436 @@ static bool spapr_nested_vcpu_check(SpaprMachineState= NestedGuest *guest, return false; } =20 - return true; + if (!inoutbuf) { + return true; + } + + /* Check to see if the in/out buffers are registered */ + if (vcpu->runbufin.addr && vcpu->runbufout.addr) { + return true; + } + + return false; +} + +static void *get_vcpu_state_ptr(SpaprMachineStateNestedGuest *guest, + target_ulong vcpuid) +{ + assert(spapr_nested_vcpu_check(guest, vcpuid, false)); + return &guest->vcpu[vcpuid].state; +} + +static void *get_vcpu_ptr(SpaprMachineStateNestedGuest *guest, + target_ulong vcpuid) +{ + assert(spapr_nested_vcpu_check(guest, vcpuid, false)); + return &guest->vcpu[vcpuid]; +} + +static void *get_guest_ptr(SpaprMachineStateNestedGuest *guest, + target_ulong vcpuid) +{ + return guest; /* for GSBE_NESTED */ +} + +/* + * set=3D1 means the L1 is trying to set some state + * set=3D0 means the L1 is trying to get some state + */ +static void copy_state_8to8(void *a, void *b, bool set) +{ + /* set takes from the Big endian element_buf and sets internal buffer = */ + + if (set) { + *(uint64_t *)a =3D be64_to_cpu(*(uint64_t *)b); + } else { + *(uint64_t *)b =3D cpu_to_be64(*(uint64_t *)a); + } +} + +static void copy_state_4to4(void *a, void *b, bool set) +{ + if (set) { + *(uint32_t *)a =3D be32_to_cpu(*(uint32_t *)b); + } else { + *(uint32_t *)b =3D cpu_to_be32(*((uint32_t *)a)); + } +} + +static void copy_state_16to16(void *a, void *b, bool set) +{ + uint64_t *src, *dst; + + if (set) { + src =3D b; + dst =3D a; + + dst[1] =3D be64_to_cpu(src[0]); + dst[0] =3D be64_to_cpu(src[1]); + } else { + src =3D a; + dst =3D b; + + dst[1] =3D cpu_to_be64(src[0]); + dst[0] =3D cpu_to_be64(src[1]); + } +} + +static void copy_state_4to8(void *a, void *b, bool set) +{ + if (set) { + *(uint64_t *)a =3D (uint64_t) be32_to_cpu(*(uint32_t *)b); + } else { + *(uint32_t *)b =3D cpu_to_be32((uint32_t) (*((uint64_t *)a))); + } +} + +static void copy_state_pagetbl(void *a, void *b, bool set) +{ + uint64_t *pagetbl; + uint64_t *buf; /* 3 double words */ + uint64_t rts; + + assert(set); + + pagetbl =3D a; + buf =3D b; + + *pagetbl =3D be64_to_cpu(buf[0]); + /* as per ISA section 6.7.6.1 */ + *pagetbl |=3D PATE0_HR; /* Host Radix bit is 1 */ + + /* RTS */ + rts =3D be64_to_cpu(buf[1]); + assert(rts =3D=3D 52); + rts =3D rts - 31; /* since radix tree size =3D 2^(RTS+31) */ + *pagetbl |=3D ((rts & 0x7) << 5); /* RTS2 is bit 56:58 */ + *pagetbl |=3D (((rts >> 3) & 0x3) << 61); /* RTS1 is bit 1:2 */ + + /* RPDS {Size =3D 2^(RPDS+3) , RPDS >=3D5} */ + *pagetbl |=3D 63 - clz64(be64_to_cpu(buf[2])) - 3; +} + +static void copy_state_proctbl(void *a, void *b, bool set) +{ + uint64_t *proctbl; + uint64_t *buf; /* 2 double words */ + + assert(set); + + proctbl =3D a; + buf =3D b; + /* PRTB: Process Table Base */ + *proctbl =3D be64_to_cpu(buf[0]); + /* PRTS: Process Table Size =3D 2^(12+PRTS) */ + if (be64_to_cpu(buf[1]) =3D=3D (1ULL << 12)) { + *proctbl |=3D 0; + } else if (be64_to_cpu(buf[1]) =3D=3D (1ULL << 24)) { + *proctbl |=3D 12; + } else { + g_assert_not_reached(); + } +} + +static void copy_state_runbuf(void *a, void *b, bool set) +{ + uint64_t *buf; /* 2 double words */ + struct SpaprMachineStateNestedGuestVcpuRunBuf *runbuf; + + assert(set); + + runbuf =3D a; + buf =3D b; + + runbuf->addr =3D be64_to_cpu(buf[0]); + assert(runbuf->addr); + + /* per spec */ + assert(be64_to_cpu(buf[1]) <=3D 16384); + + /* + * This will also hit in the input buffer but should be fine for + * now. If not we can split this function. + */ + assert(be64_to_cpu(buf[1]) >=3D VCPU_OUT_BUF_MIN_SZ); + + runbuf->size =3D be64_to_cpu(buf[1]); +} + +/* tell the L1 how big we want the output vcpu run buffer */ +static void out_buf_min_size(void *a, void *b, bool set) +{ + uint64_t *buf; /* 1 double word */ + + assert(!set); + + buf =3D b; + + buf[0] =3D cpu_to_be64(VCPU_OUT_BUF_MIN_SZ); +} + +static void copy_logical_pvr(void *a, void *b, bool set) +{ + uint32_t *buf; /* 1 word */ + uint32_t *pvr_logical_ptr; + uint32_t pvr_logical; + + pvr_logical_ptr =3D a; + buf =3D b; + + if (!set) { + buf[0] =3D cpu_to_be32(*pvr_logical_ptr); + return; + } + + pvr_logical =3D be32_to_cpu(buf[0]); + + *pvr_logical_ptr =3D pvr_logical; +} + +static void copy_tb_offset(void *a, void *b, bool set) +{ + SpaprMachineStateNestedGuest *guest; + uint64_t *buf; /* 1 double word */ + uint64_t *tb_offset_ptr; + uint64_t tb_offset; + + tb_offset_ptr =3D a; + buf =3D b; + + if (!set) { + buf[0] =3D cpu_to_be64(*tb_offset_ptr); + return; + } + + tb_offset =3D be64_to_cpu(buf[0]); + /* need to copy this to the individual tb_offset for each vcpu */ + guest =3D container_of(tb_offset_ptr, + struct SpaprMachineStateNestedGuest, + tb_offset); + for (int i =3D 0; i < guest->vcpus; i++) { + guest->vcpu[i].tb_offset =3D tb_offset; + } +} + +static void copy_state_hdecr(void *a, void *b, bool set) +{ + uint64_t *buf; /* 1 double word */ + uint64_t *hdecr_expiry_tb; + + hdecr_expiry_tb =3D a; + buf =3D b; + + if (!set) { + buf[0] =3D cpu_to_be64(*hdecr_expiry_tb); + return; + } + + *hdecr_expiry_tb =3D be64_to_cpu(buf[0]); +} + +struct guest_state_element_type guest_state_element_types[] =3D { + GUEST_STATE_ELEMENT_NOP(GSB_HV_VCPU_IGNORED_ID, 0), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR0, gpr[0]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR1, gpr[1]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR2, gpr[2]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR3, gpr[3]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR4, gpr[4]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR5, gpr[5]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR6, gpr[6]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR7, gpr[7]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR8, gpr[8]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR9, gpr[9]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR10, gpr[10]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR11, gpr[11]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR12, gpr[12]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR13, gpr[13]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR14, gpr[14]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR15, gpr[15]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR16, gpr[16]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR17, gpr[17]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR18, gpr[18]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR19, gpr[19]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR20, gpr[20]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR21, gpr[21]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR22, gpr[22]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR23, gpr[23]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR24, gpr[24]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR25, gpr[25]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR26, gpr[26]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR27, gpr[27]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR28, gpr[28]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR29, gpr[29]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR30, gpr[30]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_GPR31, gpr[31]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_NIA, nip), + GSE_ENV_DWM(GSB_VCPU_SPR_MSR, msr, HVMASK_MSR), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTR, ctr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_LR, lr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_XER, xer), + GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_CR, cr), + GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_MMCR3), + GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER2), + GUEST_STATE_ELEMENT_NOP_DW(GSB_VCPU_SPR_SIER3), + GUEST_STATE_ELEMENT_NOP_W(GSB_VCPU_SPR_WORT), + GSE_ENV_DWM(GSB_VCPU_SPR_LPCR, lpcr, HVMASK_LPCR), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMOR, amor), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HFSCR, hfscr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR0, dawr0), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX0, dawrx0), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CIABR, ciabr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PURR, purr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPURR, spurr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IC, ic), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_VTB, vtb), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HDAR, hdar), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HDSISR, hdsisr), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_HEIR, heir), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_ASDR, asdr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR0, srr0), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SRR1, srr1), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG0, sprg0), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG1, sprg1), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG2, sprg2), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SPRG3, sprg3), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PIDR, pidr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CFAR, cfar), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_PPR, ppr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAWR1, dawr1), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DAWRX1, dawrx1), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DEXCR, dexcr), + GSE_ENV_DWM(GSB_VCPU_SPR_HDEXCR, hdexcr, HVMASK_HDEXCR), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHKEYR, hashkeyr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_HASHPKEYR, hashpkeyr), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR0, vsr[0]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR1, vsr[1]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR2, vsr[2]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR3, vsr[3]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR4, vsr[4]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR5, vsr[5]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR6, vsr[6]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR7, vsr[7]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR8, vsr[8]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR9, vsr[9]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR10, vsr[10]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR11, vsr[11]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR12, vsr[12]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR13, vsr[13]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR14, vsr[14]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR15, vsr[15]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR16, vsr[16]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR17, vsr[17]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR18, vsr[18]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR19, vsr[19]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR20, vsr[20]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR21, vsr[21]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR22, vsr[22]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR23, vsr[23]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR24, vsr[24]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR25, vsr[25]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR26, vsr[26]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR27, vsr[27]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR28, vsr[28]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR29, vsr[29]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR30, vsr[30]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR31, vsr[31]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR32, vsr[32]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR33, vsr[33]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR34, vsr[34]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR35, vsr[35]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR36, vsr[36]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR37, vsr[37]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR38, vsr[38]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR39, vsr[39]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR40, vsr[40]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR41, vsr[41]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR42, vsr[42]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR43, vsr[43]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR44, vsr[44]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR45, vsr[45]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR46, vsr[46]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR47, vsr[47]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR48, vsr[48]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR49, vsr[49]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR50, vsr[50]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR51, vsr[51]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR52, vsr[52]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR53, vsr[53]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR54, vsr[54]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR55, vsr[55]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR56, vsr[56]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR57, vsr[57]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR58, vsr[58]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR59, vsr[59]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR60, vsr[60]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR61, vsr[61]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR62, vsr[62]), + GUEST_STATE_ELEMENT_ENV_QW(GSB_VCPU_SPR_VSR63, vsr[63]), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBHR, ebbhr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_TAR, tar), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_EBBRR, ebbrr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_BESCR, bescr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_IAMR, iamr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_AMR, amr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_UAMOR, uamor), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DSCR, dscr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR, fscr), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB, pspb), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL, ctrl), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR, dar), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR, dsisr), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC1, pmc1), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC2, pmc2), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC3, pmc3), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC4, pmc4), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC5, pmc5), + GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PMC6, pmc6), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR0, mmcr0), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR1, mmcr1), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCR2, mmcr2), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_MMCRA, mmcra), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SDAR , sdar), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIAR , siar), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_SIER , sier), + GUEST_STATE_ELEMENT_ENV_WW(GSB_VCPU_SPR_VSCR, vscr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FPSCR, fpscr), + GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_DEC_EXPIRE_TB, dec_expiry_tb), + GSBE_NESTED(GSB_PART_SCOPED_PAGETBL, 0x18, parttbl[0], copy_state_pag= etbl), + GSBE_NESTED(GSB_PROCESS_TBL, 0x10, parttbl[1], copy_state_pro= ctbl), + GSBE_NESTED(GSB_VCPU_LPVR, 0x4, pvr_logical, copy_logical_p= vr), + GSBE_NESTED_MSK(GSB_TB_OFFSET, 0x8, tb_offset, copy_tb_offset, + HVMASK_TB_OFFSET), + GSBE_NESTED_VCPU(GSB_VCPU_IN_BUFFER, 0x10, runbufin, copy_state_run= buf), + GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUFFER, 0x10, runbufout, copy_state_ru= nbuf), + GSBE_NESTED_VCPU(GSB_VCPU_OUT_BUF_MIN_SZ, 0x8, runbufout, out_buf_min_= size), + GSBE_NESTED_VCPU(GSB_VCPU_HDEC_EXPIRY_TB, 0x8, hdecr_expiry_tb, + copy_state_hdecr) +}; + +void spapr_nested_gsb_init(void) +{ + struct guest_state_element_type *type; + + /* Init the guest state elements lookup table, flags for now */ + for (int i =3D 0; i < ARRAY_SIZE(guest_state_element_types); i++) { + type =3D &guest_state_element_types[i]; + + assert(type->id <=3D GSB_LAST); + if (type->id >=3D GSB_VCPU_SPR_HDAR) + /* 0xf000 - 0xf005 Thread + RO */ + type->flags =3D GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY; + else if (type->id >=3D GSB_VCPU_IN_BUFFER) + /* 0x0c00 - 0xf000 Thread + RW */ + type->flags =3D 0; + else if (type->id >=3D GSB_VCPU_LPVR) + /* 0x0003 - 0x0bff Guest + RW */ + type->flags =3D GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE; + else if (type->id >=3D GSB_HV_VCPU_STATE_SIZE) + /* 0x0001 - 0x0002 Guest + RO */ + type->flags =3D GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY | + GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE; + } } =20 static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu, @@ -813,7 +1243,7 @@ static target_ulong h_guest_create_vcpu(PowerPCCPU *cp= u, l2_state->pvr =3D env->spr[SPR_PVR]; guest->vcpu[vcpuid].enabled =3D true; =20 - if (!spapr_nested_vcpu_check(guest, vcpuid)) { + if (!spapr_nested_vcpu_check(guest, vcpuid, false)) { return H_PARAMETER; } return H_SUCCESS; @@ -857,4 +1287,10 @@ void spapr_register_nested_papr(void) { /* DO NOTHING */ } + +void spapr_nested_gsb_init(void) +{ + /* DO NOTHING */ +} + #endif --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555599; cv=none; d=zohomail.com; s=zohoarc; b=atUiXwWKOUWdaPvtPpbXwwF1BLGWMJaA4FGt1D3w9Q8ivwUrY/4X4Ee0BisJKVkLs7enAi+WUebndk5uDfYiBl1meDFYvvo7JING6kkN84semUyx0bRA2+3XXOhRyXlSCI99FIUJ8Y5bqV0jo64rSVeu6HduxjymNtDjg8Mwe7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555599; 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1TGdjT157Z5TFN0IBcv6v7WnmHr+fD6gowXdxSggva2QhQ8g6u02fvWh6zgy68wUCykY 1w== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 11/15] spapr: nested: Introduce H_GUEST_[GET|SET]_STATE hcalls. Date: Thu, 18 Jan 2024 10:54:34 +0530 Message-Id: <20240118052438.1475437-12-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: zcTxsCuakXb3b0YD8CZEo7eFc00oRzxZ X-Proofpoint-ORIG-GUID: GtF_aSRcEeoRZIOpBtYz8NA8_onCDUmW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 priorityscore=1501 impostorscore=0 adultscore=0 clxscore=1015 bulkscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555600930100004 Content-Type: text/plain; charset="utf-8" Introduce the nested PAPR hcalls: - H_GUEST_GET_STATE which is used to get state of a nested guest or a guest VCPU. The value field for each element in the request is ignored and on success, will be updated to reflect current state. - H_GUEST_SET_STATE which is used to modify the state of a guest or a guest VCPU. On success, guest (or its VCPU) state shall be updated as per the value field for the requested element(s). Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr.h | 3 + include/hw/ppc/spapr_nested.h | 23 +++ hw/ppc/spapr_nested.c | 267 ++++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index fb5e8c093d..e83a9272c4 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -366,6 +366,7 @@ struct SpaprMachineState { #define H_OVERLAP -68 #define H_STATE -75 #define H_IN_USE -77 +#define H_INVALID_ELEMENT_VALUE -81 #define H_UNSUPPORTED_FLAG -256 #define H_MULTI_THREADS_ACTIVE -9005 =20 @@ -589,6 +590,8 @@ struct SpaprMachineState { #define H_GUEST_SET_CAPABILITIES 0x464 #define H_GUEST_CREATE 0x470 #define H_GUEST_CREATE_VCPU 0x474 +#define H_GUEST_GET_STATE 0x478 +#define H_GUEST_SET_STATE 0x47C #define H_GUEST_DELETE 0x488 =20 #define MAX_HCALL_OPCODE H_GUEST_DELETE diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index a71aa3fada..c124dd1455 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -225,6 +225,10 @@ typedef struct SpaprMachineStateNestedGuest { #define HVMASK_MSR 0xEBFFFFFFFFBFEFFF #define HVMASK_HDEXCR 0x00000000FFFFFFFF #define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF +#define GSB_MAX_BUF_SIZE (1024 * 1024) +#define H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE 0x8000000000000000 +#define GUEST_STATE_REQUEST_GUEST_WIDE 0x1 +#define GUEST_STATE_REQUEST_SET 0x2 =20 #define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \ .id =3D (i), \ @@ -313,6 +317,25 @@ typedef struct SpaprMachineStateNestedGuest { #define GSE_ENV_DWM(i, f, m) \ GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m) =20 +struct guest_state_element { + uint16_t id; + uint16_t size; + uint8_t value[]; +} QEMU_PACKED; + +struct guest_state_buffer { + uint32_t num_elements; + struct guest_state_element elements[]; +} QEMU_PACKED; + +/* Actual buffer plus some metadata about the request */ +struct guest_state_request { + struct guest_state_buffer *gsb; + int64_t buf; + int64_t len; + uint16_t flags; +}; + /* * Register state for entering a nested guest with H_ENTER_NESTED. * New member must be added at the end. diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 4e8b392144..dba7161563 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -8,6 +8,7 @@ #include "hw/ppc/spapr_nested.h" #include "mmu-book3s-v3.h" #include "cpu-models.h" +#include "qemu/log.h" =20 void spapr_nested_init(SpaprMachineState *spapr) { @@ -999,6 +1000,140 @@ void spapr_nested_gsb_init(void) } } =20 +static struct guest_state_element *guest_state_element_next( + struct guest_state_element *element, + int64_t *len, + int64_t *num_elements) +{ + uint16_t size; + + /* size is of element->value[] only. Not whole guest_state_element */ + size =3D be16_to_cpu(element->size); + + if (len) { + *len -=3D size + offsetof(struct guest_state_element, value); + } + + if (num_elements) { + *num_elements -=3D 1; + } + + return (struct guest_state_element *)(element->value + size); +} + +static +struct guest_state_element_type *guest_state_element_type_find(uint16_t id) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(guest_state_element_types); i++) + if (id =3D=3D guest_state_element_types[i].id) { + return &guest_state_element_types[i]; + } + + return NULL; +} + +static void log_element(struct guest_state_element *element, + struct guest_state_request *gsr) +{ + qemu_log_mask(LOG_GUEST_ERROR, "h_guest_%s_state id:0x%04x size:0x%04x= ", + gsr->flags & GUEST_STATE_REQUEST_SET ? "set" : "get", + be16_to_cpu(element->id), be16_to_cpu(element->size)); + qemu_log_mask(LOG_GUEST_ERROR, "buf:0x%016lx ...\n", + be64_to_cpu(*(uint64_t *)element->value)); +} + +static bool guest_state_request_check(struct guest_state_request *gsr) +{ + int64_t num_elements, len =3D gsr->len; + struct guest_state_buffer *gsb =3D gsr->gsb; + struct guest_state_element *element; + struct guest_state_element_type *type; + uint16_t id, size; + + /* gsb->num_elements =3D 0 =3D=3D 32 bits long */ + assert(len >=3D 4); + + num_elements =3D be32_to_cpu(gsb->num_elements); + element =3D gsb->elements; + len -=3D sizeof(gsb->num_elements); + + /* Walk the buffer to validate the length */ + while (num_elements) { + + id =3D be16_to_cpu(element->id); + size =3D be16_to_cpu(element->size); + + if (false) { + log_element(element, gsr); + } + /* buffer size too small */ + if (len < 0) { + return false; + } + + type =3D guest_state_element_type_find(id); + if (!type) { + qemu_log_mask(LOG_GUEST_ERROR,"Element ID %04x unknown\n", id); + log_element(element, gsr); + return false; + } + + if (id =3D=3D GSB_HV_VCPU_IGNORED_ID) { + goto next_element; + } + + if (size !=3D type->size) { + qemu_log_mask(LOG_GUEST_ERROR,"Size mismatch. Element ID:%04x." + "Size Exp:%i Got:%i\n", id, type->size, size); + log_element(element, gsr); + return false; + } + + if ((type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY) && + (gsr->flags & GUEST_STATE_REQUEST_SET)) { + qemu_log_mask(LOG_GUEST_ERROR,"trying to set a read-only Eleme= nt " + "ID:%04x.\n", id); + return false; + } + + if (type->flags & GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE) { + /* guest wide element type */ + if (!(gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE)) { + qemu_log_mask(LOG_GUEST_ERROR, "trying to set a guest wide= " + "Element ID:%04x.\n", id); + return false; + } + } else { + /* thread wide element type */ + if (gsr->flags & GUEST_STATE_REQUEST_GUEST_WIDE) { + qemu_log_mask(LOG_GUEST_ERROR, "trying to set a thread wid= e " + "Element ID:%04x.\n", id); + return false; + } + } +next_element: + element =3D guest_state_element_next(element, &len, &num_elements); + + } + return true; +} + +static bool is_gsr_invalid(struct guest_state_request *gsr, + struct guest_state_element *element, + struct guest_state_element_type *type) +{ + if ((gsr->flags & GUEST_STATE_REQUEST_SET) && + (*(uint64_t *)(element->value) & ~(type->mask))) { + log_element(element, gsr); + qemu_log_mask(LOG_GUEST_ERROR, "L1 can't set reserved bits i" + "(allowed mask: 0x%08lx)\n", type->mask); + return true; + } + return false; +} + static target_ulong h_guest_get_capabilities(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong opcode, @@ -1249,6 +1384,136 @@ static target_ulong h_guest_create_vcpu(PowerPCCPU = *cpu, return H_SUCCESS; } =20 +static target_ulong getset_state(SpaprMachineStateNestedGuest *guest, + uint64_t vcpuid, + struct guest_state_request *gsr) +{ + void *ptr; + uint16_t id; + struct guest_state_element *element; + struct guest_state_element_type *type; + int64_t lenleft, num_elements; + + lenleft =3D gsr->len; + + if (!guest_state_request_check(gsr)) { + return H_P3; + } + + num_elements =3D be32_to_cpu(gsr->gsb->num_elements); + element =3D gsr->gsb->elements; + /* Process the elements */ + while (num_elements) { + type =3D NULL; + /* log_element(element, gsr); */ + + id =3D be16_to_cpu(element->id); + if (id =3D=3D GSB_HV_VCPU_IGNORED_ID) { + goto next_element; + } + + type =3D guest_state_element_type_find(id); + assert(type); + + /* Get pointer to guest data to get/set */ + if (type->location && type->copy) { + ptr =3D type->location(guest, vcpuid); + assert(ptr); + if (!~(type->mask) && is_gsr_invalid(gsr, element, type)) { + return H_INVALID_ELEMENT_VALUE; + } + type->copy(ptr + type->offset, element->value, + gsr->flags & GUEST_STATE_REQUEST_SET ? true : false= ); + } + +next_element: + element =3D guest_state_element_next(element, &lenleft, &num_eleme= nts); + } + + return H_SUCCESS; +} + +static target_ulong map_and_getset_state(PowerPCCPU *cpu, + SpaprMachineStateNestedGuest *gue= st, + uint64_t vcpuid, + struct guest_state_request *gsr) +{ + target_ulong rc; + int64_t len; + bool is_write; + + len =3D gsr->len; + /* only get_state would require write access to the provided buffer */ + is_write =3D (gsr->flags & GUEST_STATE_REQUEST_SET) ? false : true; + gsr->gsb =3D address_space_map(CPU(cpu)->as, gsr->buf, (uint64_t *)&le= n, + is_write, MEMTXATTRS_UNSPECIFIED); + if (!gsr->gsb) { + rc =3D H_P3; + goto out1; + } + + if (len !=3D gsr->len) { + rc =3D H_P3; + goto out1; + } + + rc =3D getset_state(guest, vcpuid, gsr); + +out1: + address_space_unmap(CPU(cpu)->as, gsr->gsb, len, is_write, len); + return rc; +} + +static target_ulong h_guest_getset_state(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong *args, + bool set) +{ + target_ulong flags =3D args[0]; + target_ulong lpid =3D args[1]; + target_ulong vcpuid =3D args[2]; + target_ulong buf =3D args[3]; + target_ulong buflen =3D args[4]; + struct guest_state_request gsr; + SpaprMachineStateNestedGuest *guest; + + guest =3D spapr_get_nested_guest(spapr, lpid); + if (!guest) { + return H_P2; + } + gsr.buf =3D buf; + assert(buflen <=3D GSB_MAX_BUF_SIZE); + gsr.len =3D buflen; + gsr.flags =3D 0; + if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { + gsr.flags |=3D GUEST_STATE_REQUEST_GUEST_WIDE; + } + if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { + return H_PARAMETER; /* flag not supported yet */ + } + + if (set) { + gsr.flags |=3D GUEST_STATE_REQUEST_SET; + } + return map_and_getset_state(cpu, guest, vcpuid, &gsr); +} + +static target_ulong h_guest_set_state(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + return h_guest_getset_state(cpu, spapr, args, true); +} + +static target_ulong h_guest_get_state(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + return h_guest_getset_state(cpu, spapr, args, false); +} + void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); @@ -1264,6 +1529,8 @@ void spapr_register_nested_papr(void) spapr_register_hypercall(H_GUEST_CREATE , h_guest_create); spapr_register_hypercall(H_GUEST_DELETE , h_guest_delete); spapr_register_hypercall(H_GUEST_CREATE_VCPU , h_guest_create_vcpu= ); + spapr_register_hypercall(H_GUEST_SET_STATE , h_guest_set_state); + spapr_register_hypercall(H_GUEST_GET_STATE , h_guest_get_state); } =20 #else --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555686; cv=none; d=zohomail.com; s=zohoarc; b=LMSE1JGNpmxL2MpFGAK4jldQhQd0CbszyworqqHg0kj3SwKXQd2iKxMqdQSjpsHMmqb2NHG9axmi/O1lnUSCrfUak9QcIi7g5qvYz0ec2bMtEleNwhnjGmw7k2QA1rFIHdgdvUoFXiP5ulAh+VkTGjjgFE8jDewYqZoyhHQ4MU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555686; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MjN3GQdOtFm7wTjkilDoMdx45A+P6A1H9lSMoqHwTDw=; b=TtSueOmyTpj4/wzoYYpqojbd2CoxHFG21kmWDeIKaTsNTKu7oY39Qg46GjWtrOiAP2Tjp0QwiiHTVBaQ87gIxrxCJTy59wSztPglB5yABB9vuYXV9KlYw828smUjHhQDHXY1WYcn/BwZHSYfKAnMoD36Z38EpxWI9H9gmkTnKyI= ARC-Authentication-Results: i=1; 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Thu, 18 Jan 2024 05:25:18 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 40I5PFX264422362 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 18 Jan 2024 05:25:15 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 876B220040; Thu, 18 Jan 2024 05:25:15 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E8EC720043; Thu, 18 Jan 2024 05:25:13 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.in.ibm.com (unknown [9.109.243.35]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 Jan 2024 05:25:13 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=MjN3GQdOtFm7wTjkilDoMdx45A+P6A1H9lSMoqHwTDw=; b=FzQZncBAuY1D+b34iotulqFObxf378fbFcEaFu2rnJ2D/CuMLuHeOnGRkkvnxVUQhhJk QfcWDOrzja+adIs+1BwWq5mya/seUSkrkRmXMoee5GB9BX3RDgjXeiPa815k09kyIFlu Ixr1/M2SvMbZsVQZoyBt9jjHjYxrum4KSCtgxPBR1MxLa380MQ59VVzVG4G7X58T492d 4vyIZmkIdzUWG0GEpT8GJNgOU2PLAsjRksdDkryUcpLefrgc/73LuYnRv43BpD1q5X76 kQooicMjWmXHnjI5ed1rmnx6GtwygUDft0Q21L6pwASsYVjYS9dF+Vq8lbx3NTNVnxtQ 1Q== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 12/15] spapr: nested: Use correct source for parttbl info for nested PAPR API. Date: Thu, 18 Jan 2024 10:54:35 +0530 Message-Id: <20240118052438.1475437-13-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 40nqwLKqqstwy3yxciiK-J8kf7iSx0X4 X-Proofpoint-ORIG-GUID: gkIPs19sniD9nzoXntV1ZLuYIHAELzcw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=699 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555687303100003 Content-Type: text/plain; charset="utf-8" For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store partition table info, use the same in spapr_get_pate_nested() via helper. Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr_nested.h | 4 ++++ hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_nested.c | 20 +++++++++++++++++++- 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index c124dd1455..18dd82009d 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -513,4 +513,8 @@ void spapr_nested_init(SpaprMachineState *spapr); uint8_t spapr_nested_api(SpaprMachineState *spapr); void spapr_register_nested_papr(void); void spapr_nested_gsb_init(void); +bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, + target_ulong lpid, ppc_v3_pate_t *entry); +SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *sp= apr, + target_ulong lpid); #endif /* HW_SPAPR_NESTED_H */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 367beb5255..b87532343c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1379,6 +1379,8 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp= , PowerPCCPU *cpu, assert(spapr_nested_api(spapr)); if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry); + } else if (spapr_nested_api(spapr) =3D=3D NESTED_API_PAPR) { + return spapr_get_pate_nested_papr(spapr, cpu, lpid, entry); } return false; } diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index dba7161563..81c1e78323 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -52,6 +52,19 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, = PowerPCCPU *cpu, return true; } =20 +bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, + target_ulong lpid, ppc_v3_pate_t *entry) +{ + SpaprMachineStateNestedGuest *guest; + assert(lpid !=3D 0); + guest =3D spapr_get_nested_guest(spapr, lpid); + assert(guest !=3D NULL); + + entry->dw0 =3D guest->parttbl[0]; + entry->dw1 =3D guest->parttbl[1]; + return true; +} + #define PRTS_MASK 0x1f =20 static target_ulong h_set_ptbl(PowerPCCPU *cpu, @@ -536,7 +549,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) } } =20 -static SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *sp= apr, target_ulong guestid) { @@ -1550,6 +1562,12 @@ bool spapr_get_pate_nested_hv(SpaprMachineState *spa= pr, PowerPCCPU *cpu, return false; } =20 +bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, + target_ulong lpid, ppc_v3_pate_t *entry) +{ + return false; +} + void spapr_register_nested_papr(void) { /* DO NOTHING */ --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555605; cv=none; d=zohomail.com; s=zohoarc; b=DKQNvtv+a+f/Bw8nxxCB7sGax4NeQmDoPCd46WUdPR8X+TAd0GTid7UUU8U4FJWlFPSoWkxqJJL3NzgY05na/f+iUaUubCvQDewGoN2DxR5ajY/ZAwmgoz3Ld6NrXZZ/XQfFE0xu8hIGDoZN4gOvoxZuSlodRpDjWNUg4WUyHKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555605; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 18 Jan 2024 05:25:15 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=TDwb0SLPKpDa9AK6zKUsP6plMu6QlitlbEx0UjZkViA=; b=HZungadBwC6kK7r3xVX4r9Wv9YZb1pygsQL91OiuRJpMchrIiUYEM0wacGIAlpxSpA94 hthS1bjutmm6q9DDwp5wODNRseZOWqxuRXnCj0ODGiIX/s5yM8E+cXv8JBhg25ZxucDP N/+MeEmLeKEiBXt1OxYP9+AsBRWSv3mEwYnF6zXW2KcZe8jBG5MeiR7Ddu3YZQ23UzmL rW5eIbApf67cYiva3zjpJQA8EmPxYMWoURIGdv7D5fTPZMMbipWI5bOQKCVKzVQytriO lFXncJLZ7r/NKRQN7vWf6HRxshZuRSQRVSPq0ju4K+B5qC3ueo/Ype3fWh1+vB5ElKAB /w== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 13/15] spapr: nested: Introduce H_GUEST_RUN_VCPU hcall. Date: Thu, 18 Jan 2024 10:54:36 +0530 Message-Id: <20240118052438.1475437-14-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: aU6qkU5CQVbMNe1An33Qh1tSt9AVxk0o X-Proofpoint-ORIG-GUID: YKpGo-9SyYAlDof4n_uJHvthxItG9K4d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=906 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 priorityscore=1501 impostorscore=0 adultscore=0 clxscore=1015 bulkscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555606991100002 Content-Type: text/plain; charset="utf-8" The H_GUEST_RUN_VCPU hcall is used to start execution of a Guest VCPU. The Hypervisor will update the state of the Guest VCPU based on the input buffer, restore the saved Guest VCPU state, and start its execution. The Guest VCPU can stop running for numerous reasons including HCALLs, hypervisor exceptions, or an outstanding Host Partition Interrupt. The reason that the Guest VCPU stopped running is communicated through R4 and the output buffer will be filled in with any relevant state. Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr.h | 1 + target/ppc/cpu.h | 2 + hw/ppc/ppc.c | 10 ++ hw/ppc/spapr_nested.c | 333 +++++++++++++++++++++++++++++++++++++---- 4 files changed, 316 insertions(+), 30 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index e83a9272c4..4d3dbd4e7a 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -592,6 +592,7 @@ struct SpaprMachineState { #define H_GUEST_CREATE_VCPU 0x474 #define H_GUEST_GET_STATE 0x478 #define H_GUEST_SET_STATE 0x47C +#define H_GUEST_RUN_VCPU 0x480 #define H_GUEST_DELETE 0x488 =20 #define MAX_HCALL_OPCODE H_GUEST_DELETE diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index dd680178d8..e92a5307c8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1566,6 +1566,8 @@ uint64_t cpu_ppc_load_atbl(CPUPPCState *env); uint32_t cpu_ppc_load_atbu(CPUPPCState *env); void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value); void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value); +void cpu_ppc_increase_tb_by_offset (CPUPPCState *env, int64_t offset); +void cpu_ppc_decrease_tb_by_offset (CPUPPCState *env, int64_t offset); uint64_t cpu_ppc_load_vtb(CPUPPCState *env); void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value); bool ppc_decr_clear_on_delivery(CPUPPCState *env); diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index fadb8f5239..55860b9a83 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -633,6 +633,16 @@ void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t va= lue) ((uint64_t)value << 32) | tb); } =20 +void cpu_ppc_increase_tb_by_offset (CPUPPCState *env, int64_t offset) +{ + env->tb_env->tb_offset +=3D offset; +} + +void cpu_ppc_decrease_tb_by_offset (CPUPPCState *env, int64_t offset) +{ + env->tb_env->tb_offset -=3D offset; +} + uint64_t cpu_ppc_load_vtb(CPUPPCState *env) { ppc_tb_t *tb_env =3D env->tb_env; diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 81c1e78323..e7e5e72006 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -193,14 +193,28 @@ static void nested_save_state(struct nested_ppc_state= *save, PowerPCCPU *cpu) save->sier =3D env->spr[SPR_POWER_SIER]; save->vscr =3D ppc_get_vscr(env); save->fpscr =3D env->fpscr; + } else if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { + save->tb_offset =3D env->tb_env->tb_offset; } +} =20 - save->tb_offset =3D env->tb_env->tb_offset; +static void nested_post_load_state(CPUPPCState *env, CPUState *cs) +{ + /* + * compute hflags and possible interrupts. + */ + hreg_compute_hflags(env); + ppc_maybe_interrupt(env); + /* + * Nested HV does not tag TLB entries between L1 and L2, so must + * flush on transition. + */ + tlb_flush(cs); + env->reserve_addr =3D -1; /* Reset the reservation */ } =20 static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *lo= ad) { - CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); =20 @@ -279,22 +293,9 @@ static void nested_load_state(PowerPCCPU *cpu, struct = nested_ppc_state *load) env->spr[SPR_POWER_SIER] =3D load->sier; ppc_store_vscr(env, load->vscr); ppc_store_fpscr(env, load->fpscr); + } else if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { + env->tb_env->tb_offset =3D load->tb_offset; } - - env->tb_env->tb_offset =3D load->tb_offset; - - /* - * MSR updated, compute hflags and possible interrupts. - */ - hreg_compute_hflags(env); - ppc_maybe_interrupt(env); - - /* - * Nested HV does not tag TLB entries between L1 and L2, so must - * flush on transition. - */ - tlb_flush(cs); - env->reserve_addr =3D -1; /* Reset the reservation */ } =20 /* @@ -309,6 +310,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, { PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); struct nested_ppc_state l2_state; target_ulong hv_ptr =3D args[0]; @@ -407,6 +409,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, * Switch to the nested guest environment and start the "hdec" timer. */ nested_load_state(cpu, &l2_state); + nested_post_load_state(env, cs); =20 hdec =3D hv_state.hdec_expiry - now; cpu_ppc_hdecr_init(env); @@ -438,6 +441,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, static void spapr_exit_nested_hv(PowerPCCPU *cpu, int excp) { CPUPPCState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); struct nested_ppc_state l2_state; target_ulong hv_ptr =3D spapr_cpu->nested_host_state->gpr[4]; @@ -459,6 +463,7 @@ static void spapr_exit_nested_hv(PowerPCCPU *cpu, int e= xcp) */ assert(env->spr[SPR_LPIDR] !=3D 0); nested_load_state(cpu, spapr_cpu->nested_host_state); + nested_post_load_state(env, cs); env->gpr[3] =3D env->excp_vectors[excp]; /* hcall return value */ =20 cpu_ppc_hdecr_exit(env); @@ -536,19 +541,6 @@ static void spapr_exit_nested_hv(PowerPCCPU *cpu, int = excp) address_space_unmap(CPU(cpu)->as, regs, len, len, true); } =20 -void spapr_exit_nested(PowerPCCPU *cpu, int excp) -{ - SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); - SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); - - assert(spapr_cpu->in_nested); - if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { - spapr_exit_nested_hv(cpu, excp); - } else { - g_assert_not_reached(); - } -} - SpaprMachineStateNestedGuest *spapr_get_nested_guest(SpaprMachineState *sp= apr, target_ulong guestid) { @@ -1526,6 +1518,286 @@ static target_ulong h_guest_get_state(PowerPCCPU *c= pu, return h_guest_getset_state(cpu, spapr, args, false); } =20 +static void exit_nested_store_l2(PowerPCCPU *cpu, int excp, + SpaprMachineStateNestedGuestVcpu *vcpu) +{ + CPUPPCState *env =3D &cpu->env; + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + target_ulong now, hdar, hdsisr, asdr; + + assert(sizeof(env->gpr) =3D=3D sizeof(vcpu->state.gpr)); /* sanity che= ck */ + + now =3D cpu_ppc_load_tbl(env); /* L2 timebase */ + now -=3D vcpu->tb_offset; /* L1 timebase */ + vcpu->state.dec_expiry_tb =3D now - cpu_ppc_load_decr(env); + cpu_ppc_store_decr(env, spapr_cpu->nested_host_state->dec_expiry_tb - = now); + /* backup hdar, hdsisr, asdr if reqd later below */ + hdar =3D vcpu->state.hdar; + hdsisr =3D vcpu->state.hdsisr; + asdr =3D vcpu->state.asdr; + + nested_save_state(&vcpu->state, cpu); + + if (excp =3D=3D POWERPC_EXCP_MCHECK || + excp =3D=3D POWERPC_EXCP_RESET || + excp =3D=3D POWERPC_EXCP_SYSCALL) { + vcpu->state.nip =3D env->spr[SPR_SRR0]; + vcpu->state.msr =3D env->spr[SPR_SRR1] & env->msr_mask; + } else { + vcpu->state.nip =3D env->spr[SPR_HSRR0]; + vcpu->state.msr =3D env->spr[SPR_HSRR1] & env->msr_mask; + } + + /* hdar, hdsisr, asdr should be retained unless certain exceptions */ + if ((excp !=3D POWERPC_EXCP_HDSI) && (excp !=3D POWERPC_EXCP_HISI)) { + vcpu->state.asdr =3D asdr; + } else if (excp !=3D POWERPC_EXCP_HDSI) { + vcpu->state.hdar =3D hdar; + vcpu->state.hdsisr =3D hdsisr; + } +} + +static int get_exit_ids(uint64_t srr0, uint16_t ids[16]) +{ + int nr; + + switch (srr0) { + case 0xc00: + nr =3D 10; + ids[0] =3D GSB_VCPU_GPR3; + ids[1] =3D GSB_VCPU_GPR4; + ids[2] =3D GSB_VCPU_GPR5; + ids[3] =3D GSB_VCPU_GPR6; + ids[4] =3D GSB_VCPU_GPR7; + ids[5] =3D GSB_VCPU_GPR8; + ids[6] =3D GSB_VCPU_GPR9; + ids[7] =3D GSB_VCPU_GPR10; + ids[8] =3D GSB_VCPU_GPR11; + ids[9] =3D GSB_VCPU_GPR12; + break; + case 0xe00: + nr =3D 5; + ids[0] =3D GSB_VCPU_SPR_HDAR; + ids[1] =3D GSB_VCPU_SPR_HDSISR; + ids[2] =3D GSB_VCPU_SPR_ASDR; + ids[3] =3D GSB_VCPU_SPR_NIA; + ids[4] =3D GSB_VCPU_SPR_MSR; + break; + case 0xe20: + nr =3D 4; + ids[0] =3D GSB_VCPU_SPR_HDAR; + ids[1] =3D GSB_VCPU_SPR_ASDR; + ids[2] =3D GSB_VCPU_SPR_NIA; + ids[3] =3D GSB_VCPU_SPR_MSR; + break; + case 0xe40: + nr =3D 3; + ids[0] =3D GSB_VCPU_SPR_HEIR; + ids[1] =3D GSB_VCPU_SPR_NIA; + ids[2] =3D GSB_VCPU_SPR_MSR; + break; + case 0xf80: + nr =3D 3; + ids[0] =3D GSB_VCPU_SPR_HFSCR; + ids[1] =3D GSB_VCPU_SPR_NIA; + ids[2] =3D GSB_VCPU_SPR_MSR; + break; + default: + nr =3D 0; + break; + } + + return nr; +} + +static void exit_process_output_buffer(PowerPCCPU *cpu, + SpaprMachineStateNestedGuest *guest, + target_ulong vcpuid, + target_ulong *r3) +{ + SpaprMachineStateNestedGuestVcpu *vcpu =3D &guest->vcpu[vcpuid]; + struct guest_state_request gsr; + struct guest_state_buffer *gsb; + struct guest_state_element *element; + struct guest_state_element_type *type; + int exit_id_count =3D 0; + uint16_t exit_cause_ids[16]; + hwaddr len; + + len =3D vcpu->runbufout.size; + gsb =3D address_space_map(CPU(cpu)->as, vcpu->runbufout.addr, &len, tr= ue, + MEMTXATTRS_UNSPECIFIED); + if (!gsb || len !=3D vcpu->runbufout.size) { + address_space_unmap(CPU(cpu)->as, gsb, len, true, len); + *r3 =3D H_P2; + return; + } + + exit_id_count =3D get_exit_ids(*r3, exit_cause_ids); + + /* Create a buffer of elements to send back */ + gsb->num_elements =3D cpu_to_be32(exit_id_count); + element =3D gsb->elements; + for (int i =3D 0; i < exit_id_count; i++) { + type =3D guest_state_element_type_find(exit_cause_ids[i]); + assert(type); + element->id =3D cpu_to_be16(exit_cause_ids[i]); + element->size =3D cpu_to_be16(type->size); + element =3D guest_state_element_next(element, NULL, NULL); + } + gsr.gsb =3D gsb; + gsr.len =3D VCPU_OUT_BUF_MIN_SZ; + gsr.flags =3D 0; /* get + never guest wide */ + getset_state(guest, vcpuid, &gsr); + + address_space_unmap(CPU(cpu)->as, gsb, len, true, len); + return; +} + +static +void spapr_exit_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, int= excp) +{ + CPUPPCState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + target_ulong r3_return =3D env->excp_vectors[excp]; /* hcall return va= lue */ + target_ulong lpid =3D 0, vcpuid =3D 0; + struct SpaprMachineStateNestedGuestVcpu *vcpu =3D NULL; + struct SpaprMachineStateNestedGuest *guest =3D NULL; + + lpid =3D spapr_cpu->nested_host_state->gpr[5]; + vcpuid =3D spapr_cpu->nested_host_state->gpr[6]; + guest =3D spapr_get_nested_guest(spapr, lpid); + assert(guest); + spapr_nested_vcpu_check(guest, vcpuid, false); + vcpu =3D &guest->vcpu[vcpuid]; + + exit_nested_store_l2(cpu, excp, vcpu); + /* do the output buffer for run_vcpu*/ + exit_process_output_buffer(cpu, guest, vcpuid, &r3_return); + + assert(env->spr[SPR_LPIDR] !=3D 0); + nested_load_state(cpu, spapr_cpu->nested_host_state); + cpu_ppc_decrease_tb_by_offset(env, vcpu->tb_offset); + env->gpr[3] =3D H_SUCCESS; + env->gpr[4] =3D r3_return; + nested_post_load_state(env, cs); + cpu_ppc_hdecr_exit(env); + + spapr_cpu->in_nested =3D false; + g_free(spapr_cpu->nested_host_state); + spapr_cpu->nested_host_state =3D NULL; +} + +void spapr_exit_nested(PowerPCCPU *cpu, int excp) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + + assert(spapr_cpu->in_nested); + if (spapr_nested_api(spapr) =3D=3D NESTED_API_KVM_HV) { + spapr_exit_nested_hv(cpu, excp); + } else if (spapr_nested_api(spapr) =3D=3D NESTED_API_PAPR) { + spapr_exit_nested_papr(spapr, cpu, excp); + } else { + g_assert_not_reached(); + } +} + +static void nested_papr_load_l2(PowerPCCPU *cpu, + CPUPPCState *env, + SpaprMachineStateNestedGuestVcpu *vcpu, + target_ulong now) +{ + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + target_ulong lpcr, lpcr_mask, hdec; + lpcr_mask =3D LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; + + assert(vcpu); + assert(sizeof(env->gpr) =3D=3D sizeof(vcpu->state.gpr)); + nested_load_state(cpu, &vcpu->state); + lpcr =3D (env->spr[SPR_LPCR] & ~lpcr_mask) | + (vcpu->state.lpcr & lpcr_mask); + lpcr |=3D LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; + lpcr &=3D ~LPCR_LPES0; + env->spr[SPR_LPCR] =3D lpcr & pcc->lpcr_mask; + + hdec =3D vcpu->hdecr_expiry_tb - now; + cpu_ppc_store_decr(env, vcpu->state.dec_expiry_tb - now); + cpu_ppc_hdecr_init(env); + cpu_ppc_store_hdecr(env, hdec); + + cpu_ppc_increase_tb_by_offset(env, vcpu->tb_offset); +} + +static void nested_papr_run_vcpu(PowerPCCPU *cpu, + uint64_t lpid, + SpaprMachineStateNestedGuestVcpu *vcpu) +{ + SpaprMachineState *spapr =3D SPAPR_MACHINE(qdev_get_machine()); + CPUPPCState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + target_ulong now =3D cpu_ppc_load_tbl(env); + + assert(env->spr[SPR_LPIDR] =3D=3D 0); + assert(spapr->nested.api); /* ensure API version is initialized */ + spapr_cpu->nested_host_state =3D g_try_new(struct nested_ppc_state, 1); + assert(spapr_cpu->nested_host_state); + nested_save_state(spapr_cpu->nested_host_state, cpu); + spapr_cpu->nested_host_state->dec_expiry_tb =3D now - cpu_ppc_load_dec= r(env); + nested_papr_load_l2(cpu, env, vcpu, now); + env->spr[SPR_LPIDR] =3D lpid; /* post load l2 */ + + spapr_cpu->in_nested =3D true; + nested_post_load_state(env, cs); +} + +static target_ulong h_guest_run_vcpu(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong opcode, + target_ulong *args) +{ + CPUPPCState *env =3D &cpu->env; + target_ulong flags =3D args[0]; + target_ulong lpid =3D args[1]; + target_ulong vcpuid =3D args[2]; + struct SpaprMachineStateNestedGuestVcpu *vcpu; + struct guest_state_request gsr; + SpaprMachineStateNestedGuest *guest; + target_ulong rc; + + if (flags) /* don't handle any flags for now */ + return H_PARAMETER; + + guest =3D spapr_get_nested_guest(spapr, lpid); + if (!guest) { + return H_P2; + } + if (!spapr_nested_vcpu_check(guest, vcpuid, true)) { + return H_P3; + } + + if (guest->parttbl[0] =3D=3D 0) { + /* At least need a partition scoped radix tree */ + return H_NOT_AVAILABLE; + } + + vcpu =3D &guest->vcpu[vcpuid]; + + /* Read run_vcpu input buffer to update state */ + gsr.buf =3D vcpu->runbufin.addr; + gsr.len =3D vcpu->runbufin.size; + gsr.flags =3D GUEST_STATE_REQUEST_SET; /* Thread wide + writing */ + rc =3D map_and_getset_state(cpu, guest, vcpuid, &gsr); + if (rc =3D=3D H_SUCCESS) { + nested_papr_run_vcpu(cpu, lpid, vcpu); + } else { + env->gpr[3] =3D rc; + } + return env->gpr[3]; +} + void spapr_register_nested_hv(void) { spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); @@ -1543,6 +1815,7 @@ void spapr_register_nested_papr(void) spapr_register_hypercall(H_GUEST_CREATE_VCPU , h_guest_create_vcpu= ); spapr_register_hypercall(H_GUEST_SET_STATE , h_guest_set_state); spapr_register_hypercall(H_GUEST_GET_STATE , h_guest_get_state); + spapr_register_hypercall(H_GUEST_RUN_VCPU , h_guest_run_vcpu); } =20 #else --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1705555573; cv=none; d=zohomail.com; s=zohoarc; b=Oa4JkteIx3N0LQ3z14Ny2fJaQRl4QpiFpLHChmFyn/FnuBPsBfuDjlS4gQrbXH0Ap72e889R1wqjj2QcKjAtuqfcsOqPaUc8B3XrcU+jVbAloJiEE/agFdKNo8R4v8TCUDFJi+NeBqFbf+DJ1DEtYEUf+bNkH0t+IiL7mlPT9lI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705555573; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 18 Jan 2024 05:25:17 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=Fq04TSGVKhmDhp7Ea6o9blYNGK04oNML3gU/WjdIpjI=; b=cmEFoboVC6ap7HubhhjDXPYITiuRMS5SwOYBmpilANA61ImA1THICh4VNvl5Vk+WhOcQ J3iE133xkwYYLvM0TlW9qhlGFETAYNKAWwd+I/WVR5yM3zpj31/uZ1eokOgSXQtEX6R2 ClUL3gm/5CGIN6m15/3tJyDUT6amRg+QpYXThSEv3ik6Naz8mqHXzt58ityMzybCARw+ DFrrxK/j3lgaeVwlv9HIw3acRFvTuKliozc+/IGNzrQ8++/bn/m5Nd33ZFxoQhJ4rLSs Bvdi5Xcr9w2za+OTrya74BJtjAtzdoNNCuWGZtLFN4BP6fYGUbb+V3h93bh3lFgaopXp sA== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 14/15] spapr: nested: Introduce cap-nested-papr for Nested PAPR API Date: Thu, 18 Jan 2024 10:54:37 +0530 Message-Id: <20240118052438.1475437-15-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 61fNDEUnPSnkDzqTHcXPBTsD0ZjEFB9Y X-Proofpoint-ORIG-GUID: N3p_7hH5CBqf4VdVM-Dm1PnBqIUp2uNA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=743 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555574775100001 Content-Type: text/plain; charset="utf-8" Introduce a SPAPR capability cap-nested-papr which enables nested PAPR API for nested guests. This new API is to enable support for KVM on PowerVM and the support in Linux kernel has already merged upstream. Signed-off-by: Michael Neuling Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr.h | 5 +++- hw/ppc/spapr.c | 2 ++ hw/ppc/spapr_caps.c | 55 ++++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_nested.c | 2 -- 4 files changed, 61 insertions(+), 3 deletions(-) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 4d3dbd4e7a..379b64b0d7 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -81,8 +81,10 @@ typedef enum { #define SPAPR_CAP_RPT_INVALIDATE 0x0B /* Support for AIL modes */ #define SPAPR_CAP_AIL_MODE_3 0x0C +/* Nested PAPR */ +#define SPAPR_CAP_NESTED_PAPR 0x0D /* Num Caps */ -#define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1) +#define SPAPR_CAP_NUM (SPAPR_CAP_NESTED_PAPR + 1) =20 /* * Capability Values @@ -993,6 +995,7 @@ extern const VMStateDescription vmstate_spapr_cap_sbbc; extern const VMStateDescription vmstate_spapr_cap_ibs; extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; +extern const VMStateDescription vmstate_spapr_cap_nested_papr; extern const VMStateDescription vmstate_spapr_cap_large_decr; extern const VMStateDescription vmstate_spapr_cap_ccf_assist; extern const VMStateDescription vmstate_spapr_cap_fwnmi; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b87532343c..b34a1b61a6 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2120,6 +2120,7 @@ static const VMStateDescription vmstate_spapr =3D { &vmstate_spapr_cap_fwnmi, &vmstate_spapr_fwnmi, &vmstate_spapr_cap_rpt_invalidate, + &vmstate_spapr_cap_nested_papr, NULL } }; @@ -4696,6 +4697,7 @@ static void spapr_machine_class_init(ObjectClass *oc,= void *data) smc->default_caps.caps[SPAPR_CAP_IBS] =3D SPAPR_CAP_WORKAROUND; smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] =3D 16; /* 64kiB */ smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] =3D SPAPR_CAP_OFF; + smc->default_caps.caps[SPAPR_CAP_NESTED_PAPR] =3D SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] =3D SPAPR_CAP_ON; smc->default_caps.caps[SPAPR_CAP_FWNMI] =3D SPAPR_CAP_ON; diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index c3c83f6e68..4c0080120e 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -487,11 +487,56 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState= *spapr, error_append_hint(errp, "Try appending -machine cap-nested-hv= =3Doff " "or use threads=3D1 with -smp\n"); } + if (spapr->nested.api) { + warn_report("nested.api already set as %d, re-init to kvm-hv", + spapr->nested.api); + } spapr->nested.api =3D NESTED_API_KVM_HV; spapr_register_nested_hv(); } } =20 +static void cap_nested_papr_apply(SpaprMachineState *spapr, + uint8_t val, Error **errp) +{ + ERRP_GUARD(); + PowerPCCPU *cpu =3D POWERPC_CPU(first_cpu); + CPUPPCState *env =3D &cpu->env; + + if (!val) { + /* capability disabled by default */ + return; + } + + if (tcg_enabled()) { + if (!(env->insns_flags2 & PPC2_ISA300)) { + error_setg(errp, "Nested-PAPR only supported on POWER9 and lat= er"); + error_append_hint(errp, + "Try appending -machine cap-nested-papr=3Dof= f\n"); + return; + } + } else if (kvm_enabled()) { + /* + * this gets executed in L1 qemu when L2 is launched, + * needs kvm-hv support in L1 kernel. + */ + if (!kvmppc_has_cap_nested_kvm_hv()) { + error_setg(errp, + "KVM implementation does not support Nested-HV"); + } else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) { + error_setg(errp, "Error enabling Nested-HV with KVM"); + } + } + if (spapr->nested.api) { + warn_report("nested.api already set as %d, re-init to nested-papr", + spapr->nested.api); + } + spapr->nested.api =3D NESTED_API_PAPR; + spapr->nested.capabilities_set =3D false; + spapr_register_nested_papr(); + spapr_nested_gsb_init(); +} + static void cap_large_decr_apply(SpaprMachineState *spapr, uint8_t val, Error **errp) { @@ -737,6 +782,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = =3D { .type =3D "bool", .apply =3D cap_nested_kvm_hv_apply, }, + [SPAPR_CAP_NESTED_PAPR] =3D { + .name =3D "nested-papr", + .description =3D "Allow Nested HV (PAPR API)", + .index =3D SPAPR_CAP_NESTED_PAPR, + .get =3D spapr_cap_get_bool, + .set =3D spapr_cap_set_bool, + .type =3D "bool", + .apply =3D cap_nested_papr_apply, + }, [SPAPR_CAP_LARGE_DECREMENTER] =3D { .name =3D "large-decr", .description =3D "Allow Large Decrementer", @@ -921,6 +975,7 @@ SPAPR_CAP_MIG_STATE(sbbc, SPAPR_CAP_SBBC); SPAPR_CAP_MIG_STATE(ibs, SPAPR_CAP_IBS); SPAPR_CAP_MIG_STATE(hpt_maxpagesize, SPAPR_CAP_HPT_MAXPAGESIZE); SPAPR_CAP_MIG_STATE(nested_kvm_hv, SPAPR_CAP_NESTED_KVM_HV); +SPAPR_CAP_MIG_STATE(nested_papr, SPAPR_CAP_NESTED_PAPR); SPAPR_CAP_MIG_STATE(large_decr, SPAPR_CAP_LARGE_DECREMENTER); SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST); SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI); diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index e7e5e72006..b91413e09a 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -13,8 +13,6 @@ void spapr_nested_init(SpaprMachineState *spapr) { spapr->nested.api =3D 0; - spapr->nested.capabilities_set =3D false; - spapr_nested_gsb_init(); } =20 uint8_t spapr_nested_api(SpaprMachineState *spapr) --=20 2.39.3 From nobody Sat Sep 21 02:36:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 18 Jan 2024 05:25:21 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 369C520043; Thu, 18 Jan 2024 05:25:21 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9815C20040; Thu, 18 Jan 2024 05:25:19 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.in.ibm.com (unknown [9.109.243.35]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 18 Jan 2024 05:25:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=JJkX7uRZbxDZwVzvxUSOrTHXZOrNiLR6MYgW+1I/EGc=; b=VtB+Iw4pdbIhwRmOx6y9buwJi7JsjDW7pEkiTqFZgTUx0hrVv9A7N4GyGSWS1vc2dDu2 r6irN7pPghPbkjzzLQpacyMmI9k9Cn89nDPme1SytWB8zeX27EHdMru7PxBIOqTHIGYU 4fJLXzIQW0qGFA1fWjaQPeOktWOexnuPqgsJyNag099CdqxT68rZuYiJ3QQN/7OwDGUJ 8Nn1psVvht409HLahKdba9Iv4BtwbD/vAs1m38iv3fISuTUQXHqbR8cWx+LTTGe1NQxH 8yce4ieDKo6p/rOmQc0NAmj0dC3MT9FDS1zaVNHjpcqI0M2Fkhi7VIspza201ctHFJte Wg== From: Harsh Prateek Bora To: npiggin@gmail.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, clegoate@redhat.com, mikey@neuling.org, amachhiw@linux.vnet.ibm.com, vaibhav@linux.ibm.com, sbhat@linux.ibm.com, danielhb413@gmail.com Subject: [PATCH v3 15/15] spapr: nested: Set the PCR when logical PVR is set Date: Thu, 18 Jan 2024 10:54:38 +0530 Message-Id: <20240118052438.1475437-16-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240118052438.1475437-1-harshpb@linux.ibm.com> References: <20240118052438.1475437-1-harshpb@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Z08FQOxZv2Mkk5-gYXGjKg3BlzOwxaPd X-Proofpoint-ORIG-GUID: diB_anQEvy9gegSnw9pOC86eQh-dwUMO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-18_02,2024-01-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2401180035 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705555600911100001 Content-Type: text/plain; charset="utf-8" From: Amit Machhiwal In APIv1, KVM L0 sets the PCR, while in the nested papr APIv2, this doesn't work as the PCR can't be set via the guest state buffer; the logical PVR is set via the GSB though. This change sets the PCR whenever the logical PVR is set via the GSB. Also, unlike the other registers, the value 1 in a defined bit in the PCR makes the affected resources unavailable and the value 0 makes them available. Hence, the PCR is set accordingly. Signed-off-by: Amit Machhiwal Signed-off-by: Harsh Prateek Bora --- include/hw/ppc/spapr_nested.h | 9 +++++++++ hw/ppc/spapr_nested.c | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/include/hw/ppc/spapr_nested.h b/include/hw/ppc/spapr_nested.h index 18dd82009d..bdd2aa2d52 100644 --- a/include/hw/ppc/spapr_nested.h +++ b/include/hw/ppc/spapr_nested.h @@ -230,6 +230,15 @@ typedef struct SpaprMachineStateNestedGuest { #define GUEST_STATE_REQUEST_GUEST_WIDE 0x1 #define GUEST_STATE_REQUEST_SET 0x2 =20 +/* As per ISA v3.1B, following bits are reserved: + * 0:2 + * 4:57 (ISA mentions bit 58 as well but it should be used for P10) + * 61:63 (hence, haven't included PCR bits for v2.06 and v2.05 + * in LOW BITS) + */ +#define PCR_LOW_BITS (PCR_COMPAT_3_10 | PCR_COMPAT_3_00) +#define HVMASK_PCR ~PCR_LOW_BITS + #define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \ .id =3D (i), \ .size =3D (sz), \ diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index b91413e09a..75e07f454d 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -740,9 +740,11 @@ static void out_buf_min_size(void *a, void *b, bool se= t) =20 static void copy_logical_pvr(void *a, void *b, bool set) { + SpaprMachineStateNestedGuest *guest; uint32_t *buf; /* 1 word */ uint32_t *pvr_logical_ptr; uint32_t pvr_logical; + target_ulong pcr =3D 0; =20 pvr_logical_ptr =3D a; buf =3D b; @@ -755,6 +757,28 @@ static void copy_logical_pvr(void *a, void *b, bool se= t) pvr_logical =3D be32_to_cpu(buf[0]); =20 *pvr_logical_ptr =3D pvr_logical; + + if (*pvr_logical_ptr) { + switch (*pvr_logical_ptr) { + case CPU_POWERPC_LOGICAL_3_10: + pcr =3D PCR_COMPAT_3_10 | PCR_COMPAT_3_00; + break; + case CPU_POWERPC_LOGICAL_3_00: + pcr =3D PCR_COMPAT_3_00; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Could not set PCR for LPVR=3D0x%08x\n", *pvr_logical_= ptr); + return; + } + } + + guest =3D container_of(pvr_logical_ptr, + struct SpaprMachineStateNestedGuest, + pvr_logical); + for (int i =3D 0; i < guest->vcpus; i++) { + guest->vcpu[i].state.pcr =3D ~pcr | HVMASK_PCR; + } } =20 static void copy_tb_offset(void *a, void *b, bool set) --=20 2.39.3