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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=dantan@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 17 Jan 2024 23:11:26 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1705551130486100006 Content-Type: text/plain; charset="utf-8" The handling of the following two registers are added - DAWR1 (0x0bd, 189) - Data Address Watchpoint 1 DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1 Signed-off-by: dan tan --- target/ppc/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++= ++++ target/ppc/cpu.h | 6 ++++++ target/ppc/cpu_init.c | 10 ++++++++++ target/ppc/excp_helper.c | 11 ++++++++++- target/ppc/helper.h | 2 ++ target/ppc/machine.c | 1 + target/ppc/misc_helper.c | 10 ++++++++++ target/ppc/spr_common.h | 2 ++ target/ppc/translate.c | 12 ++++++++++++ 9 files changed, 104 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index e3ad8e0..8a77328 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -188,6 +188,57 @@ void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) env->spr[SPR_DAWRX0] =3D val; ppc_update_daw0(env); } + +void ppc_update_daw1(CPUPPCState *env) +{ + CPUState *cs =3D env_cpu(env); + target_ulong deaw =3D env->spr[SPR_DAWR1] & PPC_BITMASK(0, 60); + uint32_t dawrx =3D env->spr[SPR_DAWRX1]; + int mrd =3D extract32(dawrx, PPC_BIT_NR(48), 54 - 48); + bool dw =3D extract32(dawrx, PPC_BIT_NR(57), 1); + bool dr =3D extract32(dawrx, PPC_BIT_NR(58), 1); + bool hv =3D extract32(dawrx, PPC_BIT_NR(61), 1); + bool sv =3D extract32(dawrx, PPC_BIT_NR(62), 1); + bool pr =3D extract32(dawrx, PPC_BIT_NR(62), 1); + vaddr len; + int flags; + + if (env->dawr1_watchpoint) { + cpu_watchpoint_remove_by_ref(cs, env->dawr1_watchpoint); + env->dawr1_watchpoint =3D NULL; + } + + if (!dr && !dw) { + return; + } + + if (!hv && !sv && !pr) { + return; + } + + len =3D (mrd + 1) * 8; + flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + if (dr) { + flags |=3D BP_MEM_READ; + } + if (dw) { + flags |=3D BP_MEM_WRITE; + } + + cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr1_watchpoint); +} + +void ppc_store_dawr1(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_DAWR1] =3D val; + ppc_update_daw1(env); +} + +void ppc_store_dawrx1(CPUPPCState *env, uint32_t val) +{ + env->spr[SPR_DAWRX1] =3D val; + ppc_update_daw1(env); +} #endif #endif =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ff..ab34fc7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1237,6 +1237,7 @@ struct CPUArchState { ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ struct CPUBreakpoint *ciabr_breakpoint; struct CPUWatchpoint *dawr0_watchpoint; + struct CPUWatchpoint *dawr1_watchpoint; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ @@ -1552,6 +1553,9 @@ void ppc_store_ciabr(CPUPPCState *env, target_ulong v= alue); void ppc_update_daw0(CPUPPCState *env); void ppc_store_dawr0(CPUPPCState *env, target_ulong value); void ppc_store_dawrx0(CPUPPCState *env, uint32_t value); +void ppc_update_daw1(CPUPPCState *env); +void ppc_store_dawr1(CPUPPCState *env, target_ulong value); +void ppc_store_dawrx1(CPUPPCState *env, uint32_t value); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr(CPUPPCState *env, target_ulong value); =20 @@ -1737,9 +1741,11 @@ void ppc_compat_add_property(Object *obj, const char= *name, #define SPR_PSPB (0x09F) #define SPR_DPDES (0x0B0) #define SPR_DAWR0 (0x0B4) +#define SPR_DAWR1 (0x0B5) #define SPR_RPR (0x0BA) #define SPR_CIABR (0x0BB) #define SPR_DAWRX0 (0x0BC) +#define SPR_DAWRX1 (0x0BD) #define SPR_HFSCR (0x0BE) #define SPR_VRSAVE (0x100) #define SPR_USPRG0 (0x100) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 40fe14a..d75c359 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5119,11 +5119,21 @@ static void register_book3s_207_dbg_sprs(CPUPPCStat= e *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_dawr0, KVM_REG_PPC_DAWR, 0x00000000); + spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_dawr1, + KVM_REG_PPC_DAWR, 0x00000000); spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_dawrx0, KVM_REG_PPC_DAWRX, 0x00000000); + spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_dawrx1, + KVM_REG_PPC_DAWRX, 0x00000000); spr_register_kvm_hv(env, SPR_CIABR, "CIABR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a42743a..0b87b85 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3314,10 +3314,19 @@ bool ppc_cpu_debug_check_watchpoint(CPUState *cs, C= PUWatchpoint *wp) { #if defined(TARGET_PPC64) CPUPPCState *env =3D cpu_env(cs); + bool match =3D false; + uint32_t dawrx; =20 if (env->insns_flags2 & PPC2_ISA207S) { if (wp =3D=3D env->dawr0_watchpoint) { - uint32_t dawrx =3D env->spr[SPR_DAWRX0]; + dawrx =3D env->spr[SPR_DAWRX0]; + match =3D true; + } else if (wp =3D=3D env->dawr1_watchpoint) { + dawrx =3D env->spr[SPR_DAWRX1]; + match =3D true; + } + + if (match =3D=3D true) { bool wt =3D extract32(dawrx, PPC_BIT_NR(59), 1); bool wti =3D extract32(dawrx, PPC_BIT_NR(60), 1); bool hv =3D extract32(dawrx, PPC_BIT_NR(61), 1); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 86f97ee..da6ada4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -27,7 +27,9 @@ DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_ciabr, void, env, tl) DEF_HELPER_2(store_dawr0, void, env, tl) +DEF_HELPER_2(store_dawr1, void, env, tl) DEF_HELPER_2(store_dawrx0, void, env, tl) +DEF_HELPER_2(store_dawrx1, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 68cbdff..eef596d 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -326,6 +326,7 @@ static int cpu_post_load(void *opaque, int version_id) #if defined(TARGET_PPC64) ppc_update_ciabr(env); ppc_update_daw0(env); + ppc_update_daw1(env); #endif /* * TCG needs to re-start the decrementer timer and/or raise the diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index a05bdf7..1fc0705 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -209,11 +209,21 @@ void helper_store_dawr0(CPUPPCState *env, target_ulon= g value) ppc_store_dawr0(env, value); } =20 +void helper_store_dawr1(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawr1(env, value); +} + void helper_store_dawrx0(CPUPPCState *env, target_ulong value) { ppc_store_dawrx0(env, value); } =20 +void helper_store_dawrx1(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawrx1(env, value); +} + /* * DPDES register is shared. Each bit reflects the state of the * doorbell interrupt of a thread of the same core. diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 8a9d6cd..2f9b31f 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -161,7 +161,9 @@ void spr_read_cfar(DisasContext *ctx, int gprn, int spr= n); void spr_write_cfar(DisasContext *ctx, int sprn, int gprn); void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn); void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn); void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn); void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_read_purr(DisasContext *ctx, int gprn, int sprn); void spr_write_purr(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 329da4d..171e080 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -588,11 +588,23 @@ void spr_write_dawr0(DisasContext *ctx, int sprn, int= gprn) gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); } =20 +void spr_write_dawr1(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawr1(tcg_env, cpu_gpr[gprn]); +} + void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); } + +void spr_write_dawrx1(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawrx1(tcg_env, cpu_gpr[gprn]); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ =20 /* CTR */ --=20 1.8.3.1