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Wed, 17 Jan 2024 07:52:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IFs5+DR5B8fya8fOqxsWKQoHLwVJ82nv4A166ca3G/06b+5ovemqQ/hNTz9ECTpN7ZBm1P82A== X-Received: by 2002:a17:906:348b:b0:a2c:ad93:2e79 with SMTP id g11-20020a170906348b00b00a2cad932e79mr4161073ejb.15.1705506760652; Wed, 17 Jan 2024 07:52:40 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Mark Cave-Ayland , Richard Henderson Subject: [PATCH] target/i386: pcrel: store low bits of physical address in data[0] Date: Wed, 17 Jan 2024 16:51:43 +0100 Message-ID: <20240117155143.172890-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.806, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1705506801014100001 Content-Type: text/plain; charset="utf-8" For PC-relative translation blocks, env->eip changes during the execution of a translation block, Therefore, QEMU must be able to recover an instruction's PC just from the TranslationBlock struct and the instruction data with. Because a TB will not span two pages, QEMU stores all the low bits of EIP in the instruction data and replaces them in x86_restore_state_to_opc. Bits 12 and higher (which may vary between executions of a PCREL TB, since these only use the physical address in the hash key) are kept unmodified from env->eip. The assumption is that these bits of EIP, unlike bits 0-11, will not change as the translation block executes. Unfortunately, this is incorrect when the CS base is not aligned to a page. Then the linear address of the instructions (i.e. the one with the CS base addred) indeed will never span two pages, but bits 12+ of EIP can actually change. For example, if CS base is 0x80262200 and EIP =3D 0x6FF4, the first instruction in the translation block will be at linear address 0x802691F4. Even a very small TB will cross to EIP =3D 0x7xxx, while the linear addresses will remain comfortably within a single page. The fix is simply to use the low bits of the linear address for data[0], since those don't change. Then x86_restore_state_to_opc uses tb->cs_base to compute a temporary linear address (referring to some unknown instruction in the TB, but with the correct values of bits 12 and higher); the low bits are replaced with data[0], and EIP is obtained by subtracting again the CS base. Huge thanks to Mark Cave-Ayland for the image and initial debugging, and to Gitlab user @kjliew for help with bisecting another occurrence of (hopefully!) the same bug. It should be relatively easy to write a testcase that performs MMIO on an EIP with different bits 12+ than the first instruction of the translation block; any help is welcome. Fixes: e3a79e0e878 ("target/i386: Enable TARGET_TB_PCREL", 2022-10-11) Cc: qemu-stable@nongnu.org Cc: Mark Cave-Ayland Cc: Richard Henderson Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1964 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2012 Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/i386/tcg/tcg-cpu.c | 20 ++++++++++++++++---- target/i386/tcg/translate.c | 1 - 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6e881e9e276..fa956d35ecd 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -68,14 +68,26 @@ static void x86_restore_state_to_opc(CPUState *cs, X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; int cc_op =3D data[1]; + uint64_t new_pc; =20 if (tb_cflags(tb) & CF_PCREL) { - env->eip =3D (env->eip & TARGET_PAGE_MASK) | data[0]; - } else if (tb->flags & HF_CS64_MASK) { - env->eip =3D data[0]; + /* + * To ensure that bits 0..11 do not change across the translation = block, + * PC-relative TBs use linear addresses, i.e. addresses that have = the CS + * base added, for data[0]. Add the CS base back before replacing= the + * low bits, and subtract it below just like for non-PC-relative T= Bs. + */ + uint64_t pc =3D env->eip + tb->cs_base; + new_pc =3D (pc & TARGET_PAGE_MASK) | data[0]; } else { - env->eip =3D (uint32_t)(data[0] - tb->cs_base); + new_pc =3D data[0]; } + if (tb->flags & HF_CS64_MASK) { + env->eip =3D new_pc; + } else { + env->eip =3D (uint32_t)(new_pc - tb->cs_base); + } + if (cc_op !=3D CC_OP_DYNAMIC) { env->cc_op =3D cc_op; } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index cadf13bce43..e193c74472b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6996,7 +6996,6 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) =20 dc->prev_insn_end =3D tcg_last_op(); if (tb_cflags(dcbase->tb) & CF_PCREL) { - pc_arg -=3D dc->cs_base; pc_arg &=3D ~TARGET_PAGE_MASK; } tcg_gen_insn_start(pc_arg, dc->cc_op); --=20 2.43.0