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Wed, 17 Jan 2024 06:24:22 -0800 (PST) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Himanshu Chauhan Subject: [PATCH v2 1/2] target/riscv: Convert sdtrig functionality from property to an extension Date: Wed, 17 Jan 2024 19:54:11 +0530 Message-Id: <20240117142412.1615505-2-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240117142412.1615505-1-hchauhan@ventanamicro.com> References: <20240117142412.1615505-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=hchauhan@ventanamicro.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705501528346100006 Content-Type: text/plain; charset="utf-8" The debug trigger (sdtrig) capability is controlled using the debug propert= y. The sdtrig is an ISA extension and should be treated so. The sdtrig extensi= on may or may not be implemented in a system. Therefore, it must raise an ille= gal instruction exception when it is disabled and its CSRs are accessed. This patch removes the "debug" property and replaces it with ext_sdtrig ext= ension. It also raises an illegal instruction exception when the extension is disab= led and its CSRs are accessed. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 7 +++---- target/riscv/cpu_cfg.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 2 +- 5 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b07a76ef6b..c770a7e506 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -909,7 +909,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } =20 @@ -1068,7 +1068,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif @@ -1393,6 +1393,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { =20 /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { + MULTI_EXT_CFG_BOOL("x-sdtrig", ext_sdtrig, true), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), =20 @@ -1480,8 +1481,6 @@ Property riscv_cpu_options[] =3D { }; =20 static Property riscv_cpu_properties[] =3D { - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), - #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..341ebf726a 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -109,6 +109,7 @@ struct RISCVCPUConfig { bool ext_zvfbfwma; bool ext_zvfh; bool ext_zvfhmin; + bool ext_sdtrig; bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; @@ -145,7 +146,6 @@ struct RISCVCPUConfig { uint16_t cboz_blocksize; bool mmu; bool pmp; - bool debug; bool misa_w; =20 bool short_isa_string; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7e23b34f4..3f7c2f1315 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -126,7 +126,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; } =20 - if (cpu->cfg.debug && !icount_enabled()) { + if (cpu->cfg.ext_sdtrig && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c50a33397c..8dbb49aa88 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -543,7 +543,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) =20 static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 72fe2374dc..8f9787a30f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -231,7 +231,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return cpu->cfg.ext_sdtrig; } =20 static int debug_post_load(void *opaque, int version_id) --=20 2.34.1