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[81.250.175.67]) by smtp.gmail.com with ESMTPSA id d16-20020a05600c34d000b0040e83867d62sm2495316wmq.34.2024.01.16.05.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 05:02:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=adacore.com; s=google; t=1705410167; x=1706014967; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uKW/EH5R/IdiWfxo4lBBEsNkOoH1NjRDpWTKl/kBcoc=; b=k6xNufv7zNaDQNQos7UvbPT8/7OjxzUfdIPlC2Qocnqsn1+PjmqDLMltSZTc/5fatu BNXA4y5ryxqRYCXTpWSW///ZeuQrC1a1HChoqIu6xdpzipCzRYdWC5zYYSUQOMNTVF5T M2PaUYgBYdhkkELwBoDd39n0mGRhzIodti7q3jFXY1O0m8AxowDihYR2kF0OTXC4lJMx GRQR+h8gmXtB6qek2cZAHHBg/rF25xeYniThD3wf3+ZQ5RCSjJNxImzDL4+BPuxhCVAA KwsWAUhEGavjB7G6Ox2ke6yGyNcRYq8D1AqCfOsSQCxjitKkghr0uc14gfXux2BpWirP FPCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705410167; x=1706014967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uKW/EH5R/IdiWfxo4lBBEsNkOoH1NjRDpWTKl/kBcoc=; b=dRZFJc0+oBnrYU5NfVxqc52dLP6qD96E7F+ReLYCIlvGTrta9WwYEE/qpfkMSBGO0T yy/+Bo7hc5IhDPKsOxQwiJ6scy0oaJ5uTJ/cCaAHF+8O8E3EVg/5aVFWTTYODcTmmP/p mo8rhr8gacuEqPAr1AKvz0xGRXHGrBvFXIrKPiliFtv5ujGYJ2Vw2Kd4P2eVZSM05HXV GU8ALYbo8rMafOuB4tk8xqa53ydJT/FmD30NKIuhpSCVR02ljbfnebpWiAyp5C1Nc3jB EwB+bvR9qfCAIXJD8MflNSGcRpxzzgUWJquOroIRHXrkog7Anj4F7wW5a1ntSIYovJM0 l8vA== X-Gm-Message-State: AOJu0YzAYlicFXk3kr0Xi/V71hgBkzRt4AwxZMj7Z5x0wk9laBGlfVKP LGMIRipcq6uqg/flzg1gBm+bCeswYZNNoGH97ICk3puueg== X-Google-Smtp-Source: AGHT+IF52UqJcA7ULV1Nz0yPkmqu33iUQ/KzXIYB2DIhFHvgb8xIXbTptA4ppz4vwRBoVoyLRlkWNA== X-Received: by 2002:a05:600c:280b:b0:40e:44c2:92be with SMTP id m11-20020a05600c280b00b0040e44c292bemr4065008wmb.143.1705410167579; Tue, 16 Jan 2024 05:02:47 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Cl=C3=A9ment=20Chigot?= , Frederic Konrad Subject: [PATCH v2 7/8] leon3: check cpu_id in the tiny bootloader Date: Tue, 16 Jan 2024 14:02:12 +0100 Message-Id: <20240116130213.172358-8-chigot@adacore.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240116130213.172358-1-chigot@adacore.com> References: <20240116130213.172358-1-chigot@adacore.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=chigot@adacore.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @adacore.com) X-ZM-MESSAGEID: 1705410214686100002 Now that SMP is possible, the asr17 must be checked in the little boot code or the secondary CPU will reinitialize the Timer and the Uart. Co-developed-by: Frederic Konrad Signed-off-by: Cl=C3=A9ment Chigot Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/sparc/leon3.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index eacd85ee4f..87a8044a3e 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -100,13 +100,27 @@ static uint32_t *gen_store_u32(uint32_t *code, hwaddr= addr, uint32_t val) =20 /* * When loading a kernel in RAM the machine is expected to be in a differe= nt - * state (eg: initialized by the bootloader). This little code reproduces - * this behavior. + * state (eg: initialized by the bootloader). This little code reproduces + * this behavior. Also this code can be executed by the secondary cpus as + * well since it looks at the %asr17 register before doing any + * initialization, it allows to use the same reset address for all the + * cpus. */ static void write_bootloader(CPUSPARCState *env, uint8_t *base, hwaddr kernel_addr) { uint32_t *p =3D (uint32_t *) base; + uint32_t *sec_cpu_branch_p =3D NULL; + + /* If we are running on a secondary CPU, jump directly to the kernel. = */ + + stl_p(p++, 0x85444000); /* rd %asr17, %g2 */ + stl_p(p++, 0x8530a01c); /* srl %g2, 0x1c, %g2 */ + stl_p(p++, 0x80908000); /* tst %g2 */ + /* Fill that later. */ + sec_cpu_branch_p =3D p; + stl_p(p++, 0x0BADC0DE); /* bne xxx */ + stl_p(p++, 0x01000000); /* nop */ =20 /* Initialize the UARTs */ /* *UART_CONTROL =3D UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */ @@ -120,6 +134,10 @@ static void write_bootloader(CPUSPARCState *env, uint8= _t *base, /* *GPTIMER0_CONFIG =3D GPTIMER_ENABLE | GPTIMER_RESTART; */ p =3D gen_store_u32(p, 0x80000318, 3); =20 + /* Now, the relative branch above can be computed. */ + stl_p(sec_cpu_branch_p, 0x12800000 + + (p - sec_cpu_branch_p)); + /* JUMP to the entry point */ stl_p(p++, 0x82100000); /* mov %g0, %g1 */ stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22)); --=20 2.25.1