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a="13067929" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="13067929" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="874065579" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="874065579" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, yi.y.sun@intel.com, chao.p.peng@intel.com, Yu Zhang , Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv1 18/23] intel_iommu: fix the fault reason report Date: Mon, 15 Jan 2024 18:37:30 +0800 Message-Id: <20240115103735.132209-19-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115103735.132209-1-zhenzhong.duan@intel.com> References: <20240115103735.132209-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.758, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1705315323585100004 Content-Type: text/plain; charset="utf-8" From: Yu Zhang Currently we use only VTD_FR_PASID_TABLE_INV as fault reaon. Fix this with correct fault reasons listed in VT-d spec 7.2.3. Signed-off-by: Yu Zhang Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 8 ++++++- hw/i386/intel_iommu.c | 42 +++++++++++++++++++++------------- 2 files changed, 33 insertions(+), 17 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 41b958cd5d..21fa767740 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -325,8 +325,14 @@ typedef enum VTDFaultReason { * request while disabled */ VTD_FR_IR_SID_ERR =3D 0x26, /* Invalid Source-ID */ =20 - VTD_FR_PASID_TABLE_INV =3D 0x58, /*Invalid PASID table entry */ + VTD_FR_RTADDR_INV_TTM =3D 0x31, /* Invalid TTM in RTADDR */ + /* PASID directory entry access failure */ + VTD_FR_PASID_DIR_ACCESS_ERR =3D 0x50, + /* The Present(P) field of pasid directory entry is 0 */ + VTD_FR_PASID_DIR_ENTRY_P =3D 0x51, + VTD_FR_PASID_TABLE_ACCESS_ERR =3D 0x58, /* PASID table entry access fa= ilure */ VTD_FR_PASID_ENTRY_P =3D 0x59, /* The Present(P) field of pasidt-entry= is 0 */ + VTD_FR_PASID_TABLE_ENTRY_INV =3D 0x5b, /*Invalid PASID table entry */ =20 /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR =3D 0x87, diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1c21f40ccd..1e87383a41 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -819,7 +819,7 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pas= id_dir_base, addr =3D pasid_dir_base + index * entry_size; if (dma_memory_read(&address_space_memory, addr, pdire, entry_size, MEMTXATTRS_UNSPECIFIED)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_DIR_ACCESS_ERR; } =20 pdire->val =3D le64_to_cpu(pdire->val); @@ -832,6 +832,11 @@ static inline bool vtd_pe_present(VTDPASIDEntry *pe) return pe->val[0] & VTD_PASID_ENTRY_P; } =20 +static inline uint32_t vtd_pe_get_flpt_level(VTDPASIDEntry *pe) +{ + return 4 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM); +} + static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, dma_addr_t addr, @@ -840,13 +845,14 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUS= tate *s, uint32_t index; dma_addr_t entry_size; X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); + uint8_t pgtt; =20 index =3D VTD_PASID_TABLE_INDEX(pasid); entry_size =3D VTD_PASID_ENTRY_SIZE; addr =3D addr + index * entry_size; if (dma_memory_read(&address_space_memory, addr, pe, entry_size, MEMTXATTRS_UNSPECIFIED)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_TABLE_ACCESS_ERR; } for (size_t i =3D 0; i < ARRAY_SIZE(pe->val); i++) { pe->val[i] =3D le64_to_cpu(pe->val[i]); @@ -854,12 +860,17 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUS= tate *s, =20 /* Do translation type check */ if (!vtd_pe_type_check(x86_iommu, pe)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_TABLE_ENTRY_INV; } =20 - if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) { - return -VTD_FR_PASID_TABLE_INV; - } + pgtt =3D VTD_PE_GET_TYPE(pe); + if (pgtt =3D=3D VTD_SM_PASID_ENTRY_SLT && + !vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) + return -VTD_FR_PASID_TABLE_ENTRY_INV; + + if (pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT && + vtd_pe_get_flpt_level(pe) !=3D 4) + return -VTD_FR_PASID_TABLE_ENTRY_INV; =20 return 0; } @@ -899,7 +910,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, } =20 if (!vtd_pdire_present(&pdire)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_DIR_ENTRY_P; } =20 ret =3D vtd_get_pe_from_pdire(s, pasid, &pdire, pe); @@ -908,7 +919,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, } =20 if (!vtd_pe_present(pe)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_ENTRY_P; } =20 return 0; @@ -961,7 +972,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s, } =20 if (!vtd_pdire_present(&pdire)) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_PASID_DIR_ENTRY_P; } =20 /* @@ -1829,7 +1840,11 @@ static const bool vtd_qualified_faults[] =3D { [VTD_FR_ROOT_ENTRY_RSVD] =3D false, [VTD_FR_PAGING_ENTRY_RSVD] =3D true, [VTD_FR_CONTEXT_ENTRY_TT] =3D true, - [VTD_FR_PASID_TABLE_INV] =3D false, + [VTD_FR_PASID_DIR_ACCESS_ERR] =3D false, + [VTD_FR_PASID_DIR_ENTRY_P] =3D true, + [VTD_FR_PASID_TABLE_ACCESS_ERR] =3D false, + [VTD_FR_PASID_ENTRY_P] =3D true, + [VTD_FR_PASID_TABLE_ENTRY_INV] =3D true, [VTD_FR_SM_INTERRUPT_ADDR] =3D true, [VTD_FR_MAX] =3D false, }; @@ -1904,11 +1919,6 @@ static inline uint64_t vtd_flpt_level_page_mask(uint= 32_t level) return ~((1ULL << vtd_flpt_level_shift(level)) - 1); } =20 -static inline dma_addr_t vtd_pe_get_flpt_level(VTDPASIDEntry *pe) -{ - return 4 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM); -} - /* * Given an iova and the level of paging structure, return the offset * of current level. @@ -3499,7 +3509,7 @@ static inline int vtd_dev_get_pe_from_pasid(IntelIOMM= UState *s, dma_addr_t pasid_dir_base; =20 if (!s->root_scalable) { - return -VTD_FR_PASID_TABLE_INV; + return -VTD_FR_RTADDR_INV_TTM; } =20 ret =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); --=20 2.34.1