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Mon, 15 Jan 2024 05:40:48 -0500 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2024 02:40:46 -0800 Received: from spr-s2600bt.bj.intel.com ([10.240.192.124]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2024 02:40:40 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705315246; x=1736851246; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rzv4rACBfIq9ROOfL34OgDBmAl9ewK2Tn0IPg/RHhrA=; b=HRa/+nS+4B7spO4WKxgQRoB5+h314UpYpShBG0AcuEF47ekYYAbR8P3t vcOeeRSTqFRqCV94avFjnPYf7ZAgtFfx5FSdCHovA5En9Umb+TGEEePH0 OSanmgFNzmKnUuEowdOYPS7oGl/97G57Q0et8/peR/pnKmkVL7xkifwxQ gJ4Kc/Bw2yaumYjE6xSpYsbn6RjAohWF6YxHhra8HuKkWCkP0rhvZ1Aog wujhTaop3XKDwaUj7PcQrP6dSU50yITo16ZWy+bPQBJM7FcEq2YY3kk51 WqbBVAJldkCNG4ik/9n8Z5RL7uBNzs6koowsDjIGmZUKZraGFrL0qwJTO A==; X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="13067850" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="13067850" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="874065425" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="874065425" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, yi.y.sun@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv1 15/23] intel_iommu: process PASID-based Device-TLB invalidation Date: Mon, 15 Jan 2024 18:37:27 +0800 Message-Id: <20240115103735.132209-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115103735.132209-1-zhenzhong.duan@intel.com> References: <20240115103735.132209-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.758, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1705315405972100001 Content-Type: text/plain; charset="utf-8" From: Yi Liu This adds an empty handling for PASID-based Device-TLB invalidation. For now it is enough as it is not necessary to propagate it to host for passthrough device. The reason for an empty device tlb invalidation handling is that iommufd's intel vt-d cache invalidation uapi indicates all caches related to the mapping. So no need to send device tlb. spec says an iotlb invalidation should be issued before issuing device tlb invalidation. This means host should have received a cache invalidation due to guest iotlb invalidation. Hence no need to send another cache invalidation due to device tlb invalidation. Chapter 6.5.2.5: "Since translation requests-without-PASID from a device may be serviced by hardware from the IOTLB, software must always request IOTLB invalidation (iotlb_inv_dsc) before requesting corresponding Device-TLB (dev_tlb_inv_dsc) invalidation." Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index ed0d5cd99b..dcf1410fcf 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -380,6 +380,7 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descripto= r */ #define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc= */ #define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc= */ +#define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB inv_desc= */ #define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descripto= r */ =20 /* Masks for Invalidation Wait Descriptor*/ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2912fc6b88..5e7d445d98 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3950,6 +3950,17 @@ static bool vtd_process_inv_iec_desc(IntelIOMMUState= *s, return true; } =20 +static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + /* + * no need to handle it for passthru device, for emulated + * devices with device tlb, it may be required, but for now, + * return is enough + */ + return true; +} + static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -4066,6 +4077,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 + case VTD_INV_DESC_DEV_PIOTLB: + trace_vtd_inv_desc("device-piotlb", inv_desc.hi, inv_desc.lo); + if (!vtd_process_device_piotlb_desc(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_DEVICE: trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo); if (!vtd_process_device_iotlb_desc(s, &inv_desc)) { --=20 2.34.1