From nobody Tue Nov 26 20:26:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1705315284; cv=none; d=zohomail.com; s=zohoarc; b=X9s6lXYuV16uHICWu5QOI3AZHwHLdLPY9y5hs2enlgIAficBmYTvyU+r+3gIR5BXT1Rd5GopbE742EfVzEcf1/l2T9cxDE6f/YAEJDUXs+K05utjV3gB0Lbq7WW6JxClPrJHIHulj7cBlF9V3ekEOgbVAQOcLeDrkel6mCK6kiY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705315284; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=P9FgzggmUDmkdO9vZEg76h++VLhe2xE0dP7qsth4RBQ=; b=W0vW56Tau0GlcXzxPzMsUgLTvFa5xFnCh57cNeRgidW4BhcywJFxiIo+8tYUlff+C6nZRarrgZQJwrbDwXEdObkbWaYivOPY+sg9znu8sGzbuLuLWkr6pOTFjS2bNcKPNVRA9o/RXcwc3bvxYc66jYOUyq/FvzBGKBELjxBMW7o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170531528425940.88651674168568; Mon, 15 Jan 2024 02:41:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rPKOY-0002O0-E8; Mon, 15 Jan 2024 05:40:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rPKOR-0001uR-Gr for qemu-devel@nongnu.org; Mon, 15 Jan 2024 05:40:36 -0500 Received: from mgamail.intel.com ([192.198.163.8]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rPKON-0002kC-DF for qemu-devel@nongnu.org; Mon, 15 Jan 2024 05:40:34 -0500 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2024 02:40:30 -0800 Received: from spr-s2600bt.bj.intel.com ([10.240.192.124]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2024 02:40:25 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705315231; x=1736851231; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MGZbZEp7lFxf6DOJqPSLn3wam9euDL90MEGfLXGcpHM=; b=PovsC7a2OYChvgnB/3gOX2LU1nwLdqCgtjVAaJT7ctWVvQcJU4Uqpt/n aEJnGJjp3WfY4q1mkNQjbBOv0Xd1tGFivx/WOCsB6pvQYDOJr1YbVf0Xs +rx5fmo0Q5PNWykTvV9YMSFphEkI58vQ7kbbM5+vnUJNpgu/B3xqI6o6j YDjXn24Uq1K/k/WboajlTMVzLqQJc59JYHAA6ePWEdvbkAGEVu976VQt2 yd5eF3FbU+lOTr4uN5HmqKJ0Bm1KtkuHjRGrNXfU5A35cNfaxLHLhf3/O pCL6ADAIeNx2g1mBTjrgtzZbTpBRQB4wFxF45RyAcxQYU7VJoOJdT5ask g==; X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="13067747" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="13067747" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="874065368" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="874065368" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, yi.y.sun@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH rfcv1 12/23] intel_iommu: replay pasid binds after context cache invalidation Date: Mon, 15 Jan 2024 18:37:24 +0800 Message-Id: <20240115103735.132209-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115103735.132209-1-zhenzhong.duan@intel.com> References: <20240115103735.132209-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.758, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1705315285403100009 Content-Type: text/plain; charset="utf-8" From: Yi Liu This replays guest pasid attachments after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 49 ++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 3 files changed, 51 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e33c9f54b5..65fe07c13b 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -532,6 +532,7 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_FORCE_RESET =3D 0, /* pasid cache invalidation rely on guest PASID entry */ VTD_PASID_CACHE_GLOBAL_INV, + VTD_PASID_CACHE_DEVSI, VTD_PASID_CACHE_DOMSI, VTD_PASID_CACHE_PASIDSI, } VTDPCInvType; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 8f9a59ae6f..9058be9efd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -74,6 +74,10 @@ static void vtd_address_space_refresh_all(IntelIOMMUStat= e *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 static void vtd_pasid_cache_reset(IntelIOMMUState *s); +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -2102,6 +2106,8 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s) =20 static void vtd_context_global_invalidate(IntelIOMMUState *s) { + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; + trace_vtd_inv_desc_cc_global(); /* Protects context cache */ vtd_iommu_lock(s); @@ -2119,6 +2125,9 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + vtd_pasid_cache_sync(s, &pc_info); } =20 static bool iommufd_listener_skipped_section(VTDIOASContainer *container, @@ -2720,6 +2729,21 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec, context flush should also followed with PASID + * cache and iotlb flush. Regards to a device selective + * context cache invalidation: + * if (emaulted_device) + * invalidate pasid cahce and pasid-based iotlb + * else if (assigned_device) + * check if the device has been bound to any pasid + * invoke pasid_unbind regards to each bound pasid + * Here, we have vtd_pasid_cache_devsi() to invalidate pasid + * caches, while for piotlb in QEMU, we don't have it yet, so + * no handling. For assigned device, host iommu driver would + * flush piotlb when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_as->bus, devfn); } } } @@ -3351,6 +3375,12 @@ static gboolean vtd_flush_pasid(gpointer key, gpoint= er value, /* Fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->bus !=3D bus || + pc_info->devfn !=3D devfn) { + return false; + } + break; default: error_report("invalid pc_info->type"); abort(); @@ -3574,6 +3604,11 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_DEVSI: + walk_info.bus =3D pc_info->bus; + walk_info.devfn =3D pc_info->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + return; case VTD_PASID_CACHE_FORCE_RESET: /* For force reset, no need to go further replay */ return; @@ -3666,6 +3701,20 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, vtd_iommu_unlock(s); } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info =3D { .error_happened =3D false, }; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.type =3D VTD_PASID_CACHE_DEVSI; + pc_info.bus =3D bus; + pc_info.devfn =3D devfn; + + vtd_pasid_cache_sync(s, &pc_info); +} + /* Caller of this function should hold iommu_lock */ static void vtd_pasid_cache_reset(IntelIOMMUState *s) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 17e7191696..66f7c1ba59 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_reset(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation doma= in 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC in= validation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.34.1