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Mon, 15 Jan 2024 05:16:50 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2024 02:16:48 -0800 Received: from spr-s2600bt.bj.intel.com ([10.240.192.124]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2024 02:16:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705313808; x=1736849808; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jzlIz+xqyPFKX6mKgHxAxAqCZndzvcdtf7o5NBPArXY=; b=PWREvdJDLarb2PBK51Jm1XbTjgZMjUXJ0IM+/zVcbr5xS4umZPJABaXI 6cgUNf4gasnS4qrX1P8uR4Gar0PqFP9nMSh7hBzDo2uBJ1zDBNQhTF0ss aA0oFxqUO34zjb5aKOJxWODkyqa9r1wNMKMIzBOZnMOS4S7gfzGhOJOwH U9gK7rSgcO6QvjGhFsRFKUi1SkjQYAh/3tRDMTJgHaGLqqLHNEltSLFEW GzlVH2m2WAivylBDX94vdrkakz6MEMR3rX99b5Y7UzQq9frvwWNLZ8cjW CHi+3KOS8Bnvsi+aT0TNIa4EoKd4nzKoEF4zo6on/cfHOaZ/fOSKst/c/ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="390032508" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="390032508" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10953"; a="1030599517" X-IronPort-AV: E=Sophos;i="6.04,196,1695711600"; d="scan'208";a="1030599517" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, peterx@redhat.com, jasowang@redhat.com, mst@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, kevin.tian@intel.com, yi.l.liu@intel.com, yi.y.sun@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PATCH rfcv1 5/6] intel_iommu: extract out vtd_cap_init to initialize cap/ecap Date: Mon, 15 Jan 2024 18:13:12 +0800 Message-Id: <20240115101313.131139-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240115101313.131139-1-zhenzhong.duan@intel.com> References: <20240115101313.131139-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.20; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.758, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1705313845192100007 Content-Type: text/plain; charset="utf-8" This is a prerequisite for host cap/ecap sync. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 92 +++++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 42 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 95faf697eb..4c1d058ebd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4009,30 +4009,10 @@ static void vtd_iommu_replay(IOMMUMemoryRegion *iom= mu_mr, IOMMUNotifier *n) return; } =20 -/* Do the initialization. It will also be called when reset, so pay - * attention when adding new initialization stuff. - */ -static void vtd_init(IntelIOMMUState *s) +static void vtd_cap_init(IntelIOMMUState *s) { X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); =20 - memset(s->csr, 0, DMAR_REG_SIZE); - memset(s->wmask, 0, DMAR_REG_SIZE); - memset(s->w1cmask, 0, DMAR_REG_SIZE); - memset(s->womask, 0, DMAR_REG_SIZE); - - s->root =3D 0; - s->root_scalable =3D false; - s->dmar_enabled =3D false; - s->intr_enabled =3D false; - s->iq_head =3D 0; - s->iq_tail =3D 0; - s->iq =3D 0; - s->iq_size =3D 0; - s->qi_enabled =3D false; - s->iq_last_desc_type =3D VTD_INV_DESC_NONE; - s->iq_dw =3D false; - s->next_frcd_reg =3D 0; s->cap =3D VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS | VTD_CAP_MGAW(s->aw_bits); @@ -4049,27 +4029,6 @@ static void vtd_init(IntelIOMMUState *s) } s->ecap =3D VTD_ECAP_QI | VTD_ECAP_IRO; =20 - /* - * Rsvd field masks for spte - */ - vtd_spte_rsvd[0] =3D ~0ULL; - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, - x86_iommu->dt_supported); - vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); - - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, - x86_iommu->dt_sup= ported); - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, - x86_iommu->dt_sup= ported); - - if (s->scalable_mode || s->snoop_control) { - vtd_spte_rsvd[1] &=3D ~VTD_SPTE_SNP; - vtd_spte_rsvd_large[2] &=3D ~VTD_SPTE_SNP; - vtd_spte_rsvd_large[3] &=3D ~VTD_SPTE_SNP; - } - if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; if (s->intr_eim =3D=3D ON_OFF_AUTO_ON) { @@ -4102,7 +4061,56 @@ static void vtd_init(IntelIOMMUState *s) if (s->pasid) { s->ecap |=3D VTD_ECAP_PASID; } +} + +/* + * Do the initialization. It will also be called when reset, so pay + * attention when adding new initialization stuff. + */ +static void vtd_init(IntelIOMMUState *s) +{ + X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); + + memset(s->csr, 0, DMAR_REG_SIZE); + memset(s->wmask, 0, DMAR_REG_SIZE); + memset(s->w1cmask, 0, DMAR_REG_SIZE); + memset(s->womask, 0, DMAR_REG_SIZE); + + s->root =3D 0; + s->root_scalable =3D false; + s->dmar_enabled =3D false; + s->intr_enabled =3D false; + s->iq_head =3D 0; + s->iq_tail =3D 0; + s->iq =3D 0; + s->iq_size =3D 0; + s->qi_enabled =3D false; + s->iq_last_desc_type =3D VTD_INV_DESC_NONE; + s->iq_dw =3D false; + s->next_frcd_reg =3D 0; + + /* + * Rsvd field masks for spte + */ + vtd_spte_rsvd[0] =3D ~0ULL; + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); + vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supporte= d); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supporte= d); + + if (s->scalable_mode || s->snoop_control) { + vtd_spte_rsvd[1] &=3D ~VTD_SPTE_SNP; + vtd_spte_rsvd_large[2] &=3D ~VTD_SPTE_SNP; + vtd_spte_rsvd_large[3] &=3D ~VTD_SPTE_SNP; + } =20 + vtd_cap_init(s); vtd_reset_caches(s); =20 /* Define registers with default values and bit semantics */ --=20 2.34.1