From nobody Sat Sep 21 07:53:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1705236095; cv=none; d=zohomail.com; s=zohoarc; b=bgi3rQ8IIiP3w4nifF0jxxotiFhdM3TAKUBfhJD090XvhzKoqL6oADiyDmd40bVnRu8DgG/yGZT3Rogn5cnA/fz/lhM9XV8Q+zU7stLGycFvTbCSNuAGguKraDSkkL/BEjHIWR9EGzK56HXrKR25ngkLAdgwGPG9rsZIndSNqcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705236095; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DfI6LM71rZVhWLOGIPzk+FrbCZHFu6H7pIfxJhGta/0=; b=RDE8wEqVeUj+9NZBJIAWIWtnuuwli9c8BxiFd2GtMge3eTT0yO5x2vWZjYswQ5k9NL8IXuiZ1TzWbV960n7RCJiqJYgPK/+XbxcOcrWuEakNwMzgbkAIeUH+kBobcteOZ4q1nrqX07qoqmoD8+h4W3pC5EM2T6/BUNod+vajySQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705236095861320.9452754233554; Sun, 14 Jan 2024 04:41:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rOzmR-0003m1-M7; Sun, 14 Jan 2024 07:39:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOzmP-0003kA-7B; Sun, 14 Jan 2024 07:39:57 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rOzmN-0001s5-C0; Sun, 14 Jan 2024 07:39:56 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-40e68d0dbf9so19635355e9.2; Sun, 14 Jan 2024 04:39:53 -0800 (PST) Received: from archlinux.. (dynamic-077-183-249-018.77.183.pool.telefonica.de. [77.183.249.18]) by smtp.gmail.com with ESMTPSA id s2-20020a170906354200b00a293c6cc184sm4023734eja.24.2024.01.14.04.39.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jan 2024 04:39:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1705235992; x=1705840792; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DfI6LM71rZVhWLOGIPzk+FrbCZHFu6H7pIfxJhGta/0=; b=mFEGnk4SMKraZbrhVq5l1DEqWw2xUjFmSEn4ApsXqCOHXzgxoxXlf3nuyZ4K6Tzvpa pnjOzFtuXKcfu+OfUXoHSBPw9KoMY4daTJk9BKnwT5gAaXZ4+6fl90x1kidabVwImnSU rnH9tUZBGibigK8FACJ9IT0ar4AzpNh2gFpRTFYM4+8fpdiZaxAtl8adTkhohMX8w8/F 8DpTY8F6GYzpoDsBuYZM53m5ICVYGQxMhYtwMj6U7uqhv9/LyTA5YNtA9sGwLgS7UX40 4O18zeKE/pF5kp64zk9f0E+YQq15N34NuPPBlErJIxuIu7X9+9Ul06+hYan+KT4/bCEH arfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705235992; x=1705840792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DfI6LM71rZVhWLOGIPzk+FrbCZHFu6H7pIfxJhGta/0=; b=qj/zdP+jU37l8JrXSfIlOR2nmtthyPZswWpt+m/iG754nDgNiLE4HMe47kFpC81FFl 3fUqCX0SB6M+EQsihXL9VS4hLA90RdheH33MwIdPQ7wzgfwYDmhTW/ezeTW065Mc71qz ygCGWZa+BLsM1aWEH13bpCeqFwtZn7PBK4+jPjp0G8WFs63Z7FzT3tmjV9Yyu4fIV8hC Y29m92hDy0izDfhsWXi+Sd5nNB+3Rb8uVyOhpJtYAX0z7K2ieTX6TiKnja/vm4po+3Cv tP7knfA3ayhFNdECyw8/wvR0tVviFx3Al38yC7tkvQUL0LXuatvl0JcrlWLfPwyNDJI2 kEJw== X-Gm-Message-State: AOJu0YyQ1VMkGY7PZzKIa8jSSlJV3GEk8RUp8BwiJ2+uTTZttOzoPuAD 9ii4ihC84SH1cdNlQEqz6xklVAITWKw= X-Google-Smtp-Source: AGHT+IEX5gXRrWi7Qmyl7/puukbGi2JFUvxxsdiNrBsL+KX+dck3OJAu0+RZoz2mhtmhYTueaqQGYQ== X-Received: by 2002:a05:600c:4a9b:b0:40e:5be9:8ed6 with SMTP id b27-20020a05600c4a9b00b0040e5be98ed6mr1272030wmp.90.1705235991802; Sun, 14 Jan 2024 04:39:51 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-block@nongnu.org, Sergio Lopez , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Richard Henderson , qemu-ppc@nongnu.org, Artyom Tarasenko , Fabiano Rosas , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Hanna Reitz , Jiaxun Yang , John Snow , Thomas Huth , Peter Xu , Paolo Bonzini , Mark Cave-Ayland , Leonardo Bras , "Michael S. Tsirkin" , Eduardo Habkost , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Marcel Apfelbaum , BALATON Zoltan , Aleksandar Rikalo , Kevin Wolf , David Hildenbrand , Bernhard Beschow Subject: [PATCH v5 11/11] hw/isa/vt82c686: Implement relocation and toggling of SuperI/O functions Date: Sun, 14 Jan 2024 13:39:11 +0100 Message-ID: <20240114123911.4877-12-shentey@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240114123911.4877-1-shentey@gmail.com> References: <20240114123911.4877-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=shentey@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1705236097428100005 Content-Type: text/plain; charset="utf-8" The VIA south bridges are able to relocate and toggle (enable or disable) t= heir SuperI/O functions. So far this is hardcoded such that all functions are al= ways enabled and are located at fixed addresses. Some PC BIOSes seem to probe for I/O occupancy before activating such a fun= ction and issue an error in case of a conflict. Since the functions are currently enabled on reset, conflicts are always detected. Prevent that by implementi= ng relocation and toggling of the SuperI/O functions. Note that all SuperI/O functions are now deactivated upon reset (except for VT82C686B's serial ports where Fuloong 2e's rescue-yl seems to expect them = to be enabled by default). Rely on firmware to configure the functions accordingl= y. Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan --- hw/isa/vt82c686.c | 65 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index d3e0f6d01f..485bb685b7 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -15,6 +15,9 @@ =20 #include "qemu/osdep.h" #include "hw/isa/vt82c686.h" +#include "hw/block/fdc.h" +#include "hw/char/parallel-isa.h" +#include "hw/char/serial.h" #include "hw/pci/pci.h" #include "hw/qdev-properties.h" #include "hw/ide/pci.h" @@ -323,6 +326,17 @@ static uint64_t via_superio_cfg_read(void *opaque, hwa= ddr addr, unsigned size) return val; } =20 +static void via_superio_devices_enable(ViaSuperIOState *s, uint8_t data) +{ + ISASuperIOClass *ic =3D ISA_SUPERIO_GET_CLASS(s); + + isa_parallel_set_enabled(s->superio.parallel[0], (data & 0x3) !=3D 3); + for (int i =3D 0; i < ic->serial.count; i++) { + isa_serial_set_enabled(s->superio.serial[i], data & BIT(i + 2)); + } + isa_fdc_set_enabled(s->superio.floppy, data & BIT(4)); +} + static void via_superio_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -368,7 +382,25 @@ static void vt82c686b_superio_cfg_write(void *opaque, = hwaddr addr, case 0xfd ... 0xff: /* ignore write to read only registers */ return; - /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ + case 0xe2: + data &=3D 0x1f; + via_superio_devices_enable(sc, data); + break; + case 0xe3: + data &=3D 0xfc; + isa_fdc_set_iobase(sc->superio.floppy, data << 2); + break; + case 0xe6: + isa_parallel_set_iobase(sc->superio.parallel[0], data << 2); + break; + case 0xe7: + data &=3D 0xfe; + isa_serial_set_iobase(sc->superio.serial[0], data << 2); + break; + case 0xe8: + data &=3D 0xfe; + isa_serial_set_iobase(sc->superio.serial[1], data << 2); + break; default: qemu_log_mask(LOG_UNIMP, "via_superio_cfg: unimplemented register 0x%x\n", id= x); @@ -395,9 +427,14 @@ static void vt82c686b_superio_reset(DeviceState *dev) /* Device ID */ vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); - /* Function select - all disabled */ + /* + * Function select - only serial enabled + * Fuloong 2e's rescue-yl prints to the serial console w/o enabling it= . This + * suggests that the serial ports are enabled by default, so override = the + * datasheet. + */ vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); - vt82c686b_superio_cfg_write(s, 1, 0x03, 1); + vt82c686b_superio_cfg_write(s, 1, 0x0f, 1); /* Floppy ctrl base addr 0x3f0-7 */ vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); @@ -465,6 +502,21 @@ static void vt8231_superio_cfg_write(void *opaque, hwa= ddr addr, case 0xfd: /* ignore write to read only registers */ return; + case 0xf2: + data &=3D 0x17; + via_superio_devices_enable(sc, data); + break; + case 0xf4: + data &=3D 0xfe; + isa_serial_set_iobase(sc->superio.serial[0], data << 2); + break; + case 0xf6: + isa_parallel_set_iobase(sc->superio.parallel[0], data << 2); + break; + case 0xf7: + data &=3D 0xfc; + isa_fdc_set_iobase(sc->superio.floppy, data << 2); + break; default: qemu_log_mask(LOG_UNIMP, "via_superio_cfg: unimplemented register 0x%x\n", id= x); @@ -513,12 +565,6 @@ static void vt8231_superio_init(Object *obj) VIA_SUPERIO(obj)->io_ops =3D &vt8231_superio_cfg_ops; } =20 -static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio, - uint8_t index) -{ - return 0x2f8; /* FIXME: This should be settable via registers f2-f= 4 */ -} - static void vt8231_superio_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -526,7 +572,6 @@ static void vt8231_superio_class_init(ObjectClass *klas= s, void *data) =20 dc->reset =3D vt8231_superio_reset; sc->serial.count =3D 1; - sc->serial.get_iobase =3D vt8231_superio_serial_iobase; sc->parallel.count =3D 1; sc->ide.count =3D 0; /* emulated by via-ide */ sc->floppy.count =3D 1; --=20 2.43.0