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Sat, 13 Jan 2024 11:29:24 +0100 (CET) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id KmO8QdPpyo7X; Sat, 13 Jan 2024 11:29:23 +0100 (CET) Received: from localhost (localhost [IPv6:::1]) by zproxy1.enst.fr (Postfix) with ESMTP id 7BCDCC061A; Sat, 13 Jan 2024 11:29:23 +0100 (CET) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id a6nrp4H3ItXM; Sat, 13 Jan 2024 11:29:23 +0100 (CET) Received: from AM-Inspiron-3585.numericable.fr (38.162.10.109.rev.sfr.net [109.10.162.38]) by zproxy1.enst.fr (Postfix) with ESMTPSA id 37645C070E; Sat, 13 Jan 2024 11:29:23 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy1.enst.fr 7BCDCC061A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1705141763; bh=nYlucyPJjNn3tjn3l3KDjRd1roMbb90uTvgczkrDX/E=; h=From:To:Date:Message-Id:MIME-Version; b=GbvHGZtInopgkpxTGQQcKsC7UAjbCfTf6eHoU7ZHVFiJvmwWYKV4a5pwNm+X4TQOm YFICsZzv/tkFd5bk4oqLIPWCeoVoZcGjRBk2M3jimyc0UOgQrUKKsx1w/gkh4yDbLN 155FI2nNn4zkwVZwWQR4dREE1tsaH1hzL0YpLR3Q= X-Virus-Scanned: amavis at enst.fr From: Arnaud Minier To: qemu-devel@nongnu.org Cc: Alistair Francis , =?UTF-8?q?In=C3=A8s=20Varhol?= , qemu-arm@nongnu.org, Samuel Tardieu , Arnaud Minier , =?UTF-8?q?Philipe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 7/7] Add tests for the STM32L4x5_RCC Date: Sat, 13 Jan 2024 11:29:13 +0100 Message-Id: <20240113102913.18278-8-arnaud.minier@telecom-paris.fr> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240113102913.18278-1-arnaud.minier@telecom-paris.fr> References: <20240113102913.18278-1-arnaud.minier@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dc; envelope-from=arnaud.minier@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1705141886699100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol --- tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_rcc-test.c | 211 +++++++++++++++++++++++++++++++ 2 files changed, 213 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/stm32l4x5_rcc-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index a926af92f6..b0d9a8c2de 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -197,7 +197,8 @@ qtests_aspeed =3D \ =20 qtests_stm32l4x5 =3D \ ['stm32l4x5_exti-test', - 'stm32l4x5_syscfg-test'] + 'stm32l4x5_syscfg-test', + 'stm32l4x5_rcc-test'] =20 qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ diff --git a/tests/qtest/stm32l4x5_rcc-test.c b/tests/qtest/stm32l4x5_rcc-t= est.c new file mode 100644 index 0000000000..eaa2f4b02f --- /dev/null +++ b/tests/qtest/stm32l4x5_rcc-test.c @@ -0,0 +1,211 @@ +/* + * QTest testcase for STM32L4x5_RCC + * + * Copyright (c) 2023 Arnaud Minier + * Copyright (c) 2023 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/registerfields.h" +#include "libqtest-single.h" +#include "hw/misc/stm32l4x5_rcc_internals.h" + +#define RCC_BASE_ADDR 0x40021000 +#define NVIC_ISER 0xE000E100 +#define NVIC_ISPR 0xE000E200 +#define NVIC_ICPR 0xE000E280 +#define RCC_IRQ 5 + +static void enable_nvic_irq(unsigned int n) +{ + writel(NVIC_ISER, 1 << n); +} + +static void unpend_nvic_irq(unsigned int n) +{ + writel(NVIC_ICPR, 1 << n); +} + +static bool check_nvic_pending(unsigned int n) +{ + return readl(NVIC_ISPR) & (1 << n); +} + +static bool qts_wait_for_flag(QTestState *qts, uint32_t event_addr, + uint32_t flag, uint32_t value) +{ + time_t now, start =3D time(NULL); + + while (true) { + if ((qtest_readl(qts, event_addr) & flag) =3D=3D value) { + return true; + } + + /* Wait at most 5 seconds */ + now =3D time(NULL); + if (now - start > 5) { + break; + } + g_usleep(1000); + } + + return false; +} + +static bool rcc_wait_for_flag(uint32_t event_addr, uint32_t flag, + uint32_t value) +{ + return qts_wait_for_flag(global_qtest, RCC_BASE_ADDR + event_addr, fla= g, value); +} + +static void rcc_writel(unsigned int offset, uint32_t value) +{ + writel(RCC_BASE_ADDR + offset, value); +} + +static uint32_t rcc_readl(unsigned int offset) +{ + return readl(RCC_BASE_ADDR + offset); +} + +static void test_init_msi(void) +{ + /* MSIRANGE can be set only when MSI is OFF or READY */ + rcc_writel(A_CR, R_CR_MSION_MASK); + /* Wait until MSI is stable */ + g_assert_true(rcc_wait_for_flag(A_CR, R_CR_MSIRDY_MASK, R_CR_MSIRDY_MA= SK)); + /* TODO find a way to test MSI value */ +} + +static void test_set_msi_as_sysclk(void) +{ + /* Clocking from MSI, in case MSI was not the default source */ + rcc_writel(A_CFGR, 0); + /* Wait until MSI is selected and stable */ + g_assert_true(rcc_wait_for_flag(A_CFGR, R_CFGR_SWS_MASK, 0)); +} + +static void test_init_pll(void) +{ + uint32_t value; + + /* + * Update PLL and set MSI as the source clock. + * PLLM =3D 1 --> 000 + * PLLN =3D 40 --> 40 + * PPLLR =3D 2 --> 00 + * PLLDIV =3D unused, PLLP =3D unused (SAI3), PLLQ =3D unused (48M1) + * SRC =3D MSI --> 01 + */ + rcc_writel(A_PLLCFGR, R_PLLCFGR_PLLREN_MASK | + (40 << R_PLLCFGR_PLLN_SHIFT) | + (0b01 << R_PLLCFGR_PLLSRC_SHIFT)); + + /* PLL activation */ + value =3D rcc_readl(A_CR); + rcc_writel(A_CR, value | R_CR_PLLON_MASK); + + /* Waiting for PLL lock. */ + g_assert_true(rcc_wait_for_flag(A_CR, R_CR_PLLRDY_MASK, R_CR_PLLRDY_MA= SK)); + + /* Switches on the PLL clock source */ + value =3D rcc_readl(A_CFGR); + rcc_writel(A_CFGR, (value & ~R_CFGR_SW_MASK) | + (0b11 << R_CFGR_SW_SHIFT)); + + /* Wait until SYSCLK is stable. */ + g_assert_true(rcc_wait_for_flag(A_CFGR, R_CFGR_SWS_MASK, + (0b11 << R_CFGR_SWS_SHIFT))); +} + +static void test_activate_lse(void) +{ + /* LSE activation, no LSE Bypass */ + rcc_writel(A_BDCR, R_BDCR_LSEDRV_MASK | R_BDCR_LSEON_MASK); + g_assert_true(rcc_wait_for_flag(A_BDCR, R_BDCR_LSERDY_MASK, R_BDCR_LSE= RDY_MASK)); +} + +static void test_irq(void) +{ + enable_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_LSIRDYIE_MASK); + rcc_writel(A_CSR, R_CSR_LSION_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_LSIRDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_LSERDYIE_MASK); + rcc_writel(A_BDCR, R_BDCR_LSEON_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_LSERDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_MSIRDYIE_MASK); + rcc_writel(A_CR, R_CR_MSION_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_MSIRDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_HSIRDYIE_MASK); + rcc_writel(A_CR, R_CR_HSION_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_HSIRDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_HSERDYIE_MASK); + rcc_writel(A_CR, R_CR_HSEON_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_HSERDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_PLLRDYIE_MASK); + rcc_writel(A_CR, R_CR_PLLON_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_PLLRDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_PLLSAI1RDYIE_MASK); + rcc_writel(A_CR, R_CR_PLLSAI1ON_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_PLLSAI1RDYC_MASK); + unpend_nvic_irq(RCC_IRQ); + + rcc_writel(A_CIER, R_CIER_PLLSAI2RDYIE_MASK); + rcc_writel(A_CR, R_CR_PLLSAI2ON_MASK); + g_assert_true(check_nvic_pending(RCC_IRQ)); + rcc_writel(A_CICR, R_CICR_PLLSAI2RDYC_MASK); + unpend_nvic_irq(RCC_IRQ); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + g_test_set_nonfatal_assertions(); + /* + * These test separately that we can enable the plls, change the syscl= k, + * and enable different devices. + * They are dependent on one another. + * The procedure is taken from a program by Samuel Tardieu. + */ + qtest_add_func("stm32l4x5/rcc/init_msi", test_init_msi); + qtest_add_func("stm32l4x5/rcc/set_msi_as_sysclk", + test_set_msi_as_sysclk); + qtest_add_func("stm32l4x5/rcc/activate_lse", test_activate_lse); + qtest_add_func("stm32l4x5/rcc/init_pll", test_init_pll); + + qtest_add_func("stm32l4x5/rcc/irq", test_irq); + + qtest_start("-machine b-l475e-iot01a"); + ret =3D g_test_run(); + qtest_end(); + + return ret; +} --=20 2.34.1