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Fri, 12 Jan 2024 06:02:34 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 8/8] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:02:01 -0300 Message-ID: <20240112140201.127083-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068263486100011 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 110 +++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab77649c4c..ad1df2318b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2050,6 +2050,62 @@ static const PropertyInfo prop_mimpid =3D { .set =3D prop_mimpid_set, }; =20 +static void prop_marchid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void prop_marchid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_marchid =3D { + .name =3D "marchid", + .get =3D prop_marchid_get, + .set =3D prop_marchid_set, +}; + /* * RVA22U64 defines some 'named features' or 'synthetic extensions' * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa @@ -2138,6 +2194,7 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, {.name =3D "mimpid", .info =3D &prop_mimpid}, + {.name =3D "marchid", .info =3D &prop_marchid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2219,56 +2276,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.marchid; - uint64_t value, invalid_val; - uint32_t mxlen =3D 0; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - switch (riscv_cpu_mxl(&cpu->env)) { - case MXL_RV32: - mxlen =3D 32; - break; - case MXL_RV64: - case MXL_RV128: - mxlen =3D 64; - break; - default: - g_assert_not_reached(); - } - - invalid_val =3D 1LL << (mxlen - 1); - - if (value =3D=3D invalid_val) { - error_setg(errp, "Unable to set marchid with MSB (%u) bit set " - "and the remaining bits zero", mxlen); - return; - } - - cpu->cfg.marchid =3D value; -} - -static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; - - visit_type_uint64(v, name, &value, errp); -} - static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2299,9 +2306,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, - cpu_set_marchid, NULL, NULL); - device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.43.0