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Fri, 12 Jan 2024 06:02:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v5 1/8] target/riscv: create finalize_features() for KVM Date: Fri, 12 Jan 2024 11:01:54 -0300 Message-ID: <20240112140201.127083-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068331959100007 Content-Type: text/plain; charset="utf-8" To turn cbom_blocksize and cboz_blocksize into class properties we need KVM specific changes. KVM is creating its own version of these options with a customized setter() that prevents users from picking an invalid value during init() time. This comes at the cost of duplicating each option that KVM supports. This will keep happening for each new shared option KVM implements in the future. We can avoid that by using the same property TCG uses and adding specific KVM handling during finalize() time, like TCG already does with riscv_tcg_cpu_finalize_features(). To do that, the common CPU property offers a way of knowing if an option was user set or not, sparing us from doing unneeded syscalls. riscv_kvm_cpu_finalize_features() is then created using the same KVMScratch CPU we already use during init() time, since finalize() time is still too early to use the official KVM CPU for it. cbom_blocksize and cboz_blocksize are then handled during finalize() in the same way they're handled by their KVM specific setter. With this change we can proceed with the blocksize changes in the common code without breaking the KVM driver. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 16 +++++++--- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 59 ++++++++++++++++++++++++++++++++++++ target/riscv/kvm/kvm_riscv.h | 1 + 4 files changed, 72 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8d3ec74a1c..d64fce5a73 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -68,6 +68,11 @@ static void cpu_option_add_user_setting(const char *optn= ame, uint32_t value) GUINT_TO_POINTER(value)); } =20 +bool riscv_cpu_option_set(const char *optname) +{ + return g_hash_table_contains(general_user_opts, optname); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1109,17 +1114,18 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) } #endif =20 - /* - * KVM accel does not have a specialized finalize() - * callback because its extensions are validated - * in the get()/set() callbacks of each property. - */ if (tcg_enabled()) { riscv_tcg_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } + } else if (kvm_enabled()) { + riscv_kvm_cpu_finalize_features(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } } =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11df226a00..2dc28429e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -510,6 +510,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); +bool riscv_cpu_option_set(const char *optname); =20 #define cpu_mmu_index riscv_cpu_mmu_index =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 680a729cd8..dc0466df69 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1598,6 +1598,65 @@ static bool kvm_cpu_realize(CPUState *cs, Error **er= rp) return true; } =20 +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + KVMScratchCPU kvmcpu; + struct kvm_one_reg reg; + uint64_t val; + int ret; + + /* short-circuit without spinning the scratch CPU */ + if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz) { + return; + } + + if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { + error_setg(errp, "Unable to create scratch KVM cpu"); + return; + } + + if (cpu->cfg.ext_zicbom && + riscv_cpu_option_set(kvm_cbom_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cbom_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cbom_blocksize !=3D val) { + error_setg(errp, "Unable to set cbom_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + if (cpu->cfg.ext_zicboz && + riscv_cpu_option_set(kvm_cboz_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cboz_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cboz_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cboz_blocksize !=3D val) { + error_setg(errp, "Unable to set cboz_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + kvm_riscv_destroy_scratch_vcpu(&kvmcpu); +} + static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 8329cfab82..4bd98fddc7 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -27,5 +27,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state); +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); =20 #endif --=20 2.43.0 From nobody Sun Nov 10 22:21:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 12 Jan 2024 06:02:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 2/8] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:01:55 -0300 Message-ID: <20240112140201.127083-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068243563100008 Content-Type: text/plain; charset="utf-8" After adding a KVM finalize() implementation, turn cbom_blocksize into a class property. Follow the same design we used with 'vlen' and 'elen'. The duplicated 'cbom_blocksize' KVM property can be removed from kvm_riscv_add_cpu_user_properties(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 4 ---- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d64fce5a73..0391f16e28 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1321,6 +1321,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); cpu->cfg.vlen =3D 128; cpu->cfg.elen =3D 64; + cpu->cfg.cbom_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1872,8 +1873,42 @@ static const PropertyInfo prop_elen =3D { .set =3D prop_elen_set, }; =20 +static void prop_cbom_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (value !=3D cpu->cfg.cbom_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cbom_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cbom_blocksize =3D value; +} + +static void prop_cbom_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cbom_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cbom_blksize =3D { + .name =3D "cbom_blocksize", + .get =3D prop_cbom_blksize_get, + .set =3D prop_cbom_blksize_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 @@ -1962,6 +1997,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "vlen", .info =3D &prop_vlen}, {.name =3D "elen", .info =3D &prop_elen}, =20 + {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index dc0466df69..094bc5f47c 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -493,10 +493,6 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) NULL, multi_cfg); } =20 - object_property_add(cpu_obj, "cbom_blocksize", "uint16", - NULL, kvm_cpu_set_cbomz_blksize, - NULL, &kvm_cbom_blocksize); - object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); --=20 2.43.0 From nobody Sun Nov 10 22:21:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705068259; cv=none; d=zohomail.com; s=zohoarc; b=MdWhuj3t+48o1r9fNVEoYWN5FlJVi03QCKaXj3W1/tJFMQh53dbqve3G09fEOxYLgR7oyyFCVIyGZ8FhNcNHk1C9U1pC7Oyw5wazaNOGKl3gki5eGCZ+uHDMp94wU76vZCGV745AYT/GW7kSqPd+K6n1zPQOhFMdMjH8zcB3B+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705068259; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 12 Jan 2024 06:02:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 3/8] target/riscv: move 'cbop_blocksize' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:01:56 -0300 Message-ID: <20240112140201.127083-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068261629100006 Content-Type: text/plain; charset="utf-8" Do the same we did with 'cbom_blocksize' in the previous patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0391f16e28..8976dc26a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1322,6 +1322,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.vlen =3D 128; cpu->cfg.elen =3D 64; cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1908,8 +1909,42 @@ static const PropertyInfo prop_cbom_blksize =3D { .set =3D prop_cbom_blksize_set, }; =20 +static void prop_cbop_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (value !=3D cpu->cfg.cbop_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cbop_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cbop_blocksize =3D value; +} + +static void prop_cbop_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cbop_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cbop_blksize =3D { + .name =3D "cbop_blocksize", + .get =3D prop_cbop_blksize_get, + .set =3D prop_cbop_blksize_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), @@ -1998,6 +2033,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "elen", .info =3D &prop_elen}, =20 {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize}, + {.name =3D "cbop_blocksize", .info =3D &prop_cbop_blksize}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), --=20 2.43.0 From nobody Sun Nov 10 22:21:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 12 Jan 2024 06:02:22 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 4/8] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:01:57 -0300 Message-ID: <20240112140201.127083-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068261615100005 Content-Type: text/plain; charset="utf-8" And remove the now unused kvm_cpu_set_cbomz_blksize() setter. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 28 ---------------------------- 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8976dc26a3..ce4fdfaf0e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1323,6 +1323,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.elen =3D 64; cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1944,8 +1945,42 @@ static const PropertyInfo prop_cbop_blksize =3D { .set =3D prop_cbop_blksize_set, }; =20 +static void prop_cboz_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (value !=3D cpu->cfg.cboz_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cboz_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cboz_blocksize =3D value; +} + +static void prop_cboz_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cboz_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cboz_blksize =3D { + .name =3D "cboz_blocksize", + .get =3D prop_cboz_blksize_get, + .set =3D prop_cboz_blksize_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), }; @@ -2034,6 +2069,7 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize}, {.name =3D "cbop_blocksize", .info =3D &prop_cbop_blksize}, + {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 094bc5f47c..748a690b73 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -352,30 +352,6 @@ static KVMCPUConfig kvm_cboz_blocksize =3D { .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 -static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - KVMCPUConfig *cbomz_cfg =3D opaque; - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint16_t value, *host_val; - - if (!visit_type_uint16(v, name, &value, errp)) { - return; - } - - host_val =3D kvmconfig_get_cfg_addr(cpu, cbomz_cfg); - - if (value !=3D *host_val) { - error_report("Unable to set %s to a different value than " - "the host (%u)", - cbomz_cfg->name, *host_val); - exit(EXIT_FAILURE); - } - - cbomz_cfg->user_set =3D true; -} - static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { CPURISCVState *env =3D &cpu->env; @@ -493,10 +469,6 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) NULL, multi_cfg); } =20 - object_property_add(cpu_obj, "cboz_blocksize", "uint16", - NULL, kvm_cpu_set_cbomz_blksize, - NULL, &kvm_cboz_blocksize); - riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 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Fri, 12 Jan 2024 06:02:25 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 5/8] target/riscv: remove riscv_cpu_options[] Date: Fri, 12 Jan 2024 11:01:58 -0300 Message-ID: <20240112140201.127083-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068243535100007 Content-Type: text/plain; charset="utf-8" The array is empty and can be removed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 5 ----- target/riscv/cpu.h | 1 - target/riscv/kvm/kvm-cpu.c | 9 --------- target/riscv/tcg/tcg-cpu.c | 4 ---- 4 files changed, 19 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce4fdfaf0e..be5fa13df1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1980,11 +1980,6 @@ static const PropertyInfo prop_cboz_blksize =3D { .set =3D prop_cboz_blksize_set, }; =20 -Property riscv_cpu_options[] =3D { - - DEFINE_PROP_END_OF_LIST(), -}; - /* * RVA22U64 defines some 'named features' or 'synthetic extensions' * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dc28429e6..0ed6879a9b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -790,7 +790,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_ex= ts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; -extern Property riscv_cpu_options[]; =20 typedef struct isa_ext_data { const char *name; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 748a690b73..4dec91740b 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1527,19 +1527,10 @@ void kvm_riscv_aia_create(MachineState *machine, ui= nt64_t group_shift, static void kvm_cpu_instance_init(CPUState *cs) { Object *obj =3D OBJECT(RISCV_CPU(cs)); - DeviceState *dev =3D DEVICE(obj); =20 riscv_init_kvm_registers(obj); =20 kvm_riscv_add_cpu_user_properties(obj); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - /* Check if we have a specific KVM handler for the option */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } } =20 /* diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index daff0b8f60..ea68182426 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -1301,10 +1301,6 @@ static void riscv_cpu_add_user_properties(Object *ob= j) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); =20 riscv_cpu_add_profiles(obj); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - qdev_property_add_static(DEVICE(obj), prop); - } } =20 /* --=20 2.43.0 From nobody Sun Nov 10 22:21:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705068272; cv=none; d=zohomail.com; s=zohoarc; b=VR8Vs/qhUszS51ne/4EfJqyR8Hmzh3EtdBd7EtaBxeL8KF2ie6YajwoF0H6lOVjH4z7ix8LYMMT3BcjcvLPtwxX9+D/nTrjhyADHihuGQfw+KUa+SuyIqf1dzvkpyGBnfTGxslQQuhfxy9VAeEvPEtVcoioJoUfFzxPo+fSX2K0= ARC-Message-Signature: i=1; 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Fri, 12 Jan 2024 06:02:28 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 6/8] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:01:59 -0300 Message-ID: <20240112140201.127083-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068273501100001 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 69 +++++++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index be5fa13df1..3adc3a04f8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1980,6 +1980,41 @@ static const PropertyInfo prop_cboz_blksize =3D { .set =3D prop_cboz_blksize_set, }; =20 +static void prop_mvendorid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint32_t prev_val =3D cpu->cfg.mvendorid; + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mvendorid (0x%x)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mvendorid =3D value; +} + +static void prop_mvendorid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint32_t value =3D RISCV_CPU(obj)->cfg.mvendorid; + + visit_type_uint32(v, name, &value, errp); +} + +static const PropertyInfo prop_mvendorid =3D { + .name =3D "mvendorid", + .get =3D prop_mvendorid_get, + .set =3D prop_mvendorid_set, +}; + /* * RVA22U64 defines some 'named features' or 'synthetic extensions' * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa @@ -2066,6 +2101,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "cbop_blocksize", .info =3D &prop_cbop_blksize}, {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize}, =20 + {.name =3D "mvendorid", .info =3D &prop_mvendorid}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif @@ -2146,35 +2183,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t prev_val =3D cpu->cfg.mvendorid; - uint32_t value; - - if (!visit_type_uint32(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s mvendorid (0x%x)", - object_get_typename(obj), prev_val); - return; - } - - cpu->cfg.mvendorid =3D value; -} - -static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint32_t value =3D RISCV_CPU(obj)->cfg.mvendorid; - - visit_type_uint32(v, name, &value, errp); -} - static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2284,9 +2292,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, - cpu_set_mvendorid, NULL, NULL); - object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, cpu_set_mimpid, NULL, NULL); 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Fri, 12 Jan 2024 06:02:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 7/8] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:02:00 -0300 Message-ID: <20240112140201.127083-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068243568100009 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 68 ++++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3adc3a04f8..ab77649c4c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2015,6 +2015,41 @@ static const PropertyInfo prop_mvendorid =3D { .set =3D prop_mvendorid_set, }; =20 +static void prop_mimpid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void prop_mimpid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_mimpid =3D { + .name =3D "mimpid", + .get =3D prop_mimpid_get, + .set =3D prop_mimpid_set, +}; + /* * RVA22U64 defines some 'named features' or 'synthetic extensions' * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa @@ -2102,6 +2137,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize}, =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, + {.name =3D "mimpid", .info =3D &prop_mimpid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2183,35 +2219,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.mimpid; - uint64_t value; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - cpu->cfg.mimpid =3D value; -} - -static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.mimpid; - - visit_type_uint64(v, name, &value, errp); -} - static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2292,9 +2299,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, - cpu_set_mimpid, NULL, NULL); - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, cpu_set_marchid, NULL, NULL); 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Fri, 12 Jan 2024 06:02:34 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Vladimir Isaev Subject: [PATCH v5 8/8] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] Date: Fri, 12 Jan 2024 11:02:01 -0300 Message-ID: <20240112140201.127083-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240112140201.127083-1-dbarboza@ventanamicro.com> References: <20240112140201.127083-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1705068263486100011 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Tested-by: Vladimir Isaev tested-by tags added, rebased with Alistair's riscv-to-apply.next. --- target/riscv/cpu.c | 110 +++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab77649c4c..ad1df2318b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2050,6 +2050,62 @@ static const PropertyInfo prop_mimpid =3D { .set =3D prop_mimpid_set, }; =20 +static void prop_marchid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void prop_marchid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_marchid =3D { + .name =3D "marchid", + .get =3D prop_marchid_get, + .set =3D prop_marchid_set, +}; + /* * RVA22U64 defines some 'named features' or 'synthetic extensions' * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa @@ -2138,6 +2194,7 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, {.name =3D "mimpid", .info =3D &prop_mimpid}, + {.name =3D "marchid", .info =3D &prop_marchid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2219,56 +2276,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.marchid; - uint64_t value, invalid_val; - uint32_t mxlen =3D 0; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - switch (riscv_cpu_mxl(&cpu->env)) { - case MXL_RV32: - mxlen =3D 32; - break; - case MXL_RV64: - case MXL_RV128: - mxlen =3D 64; - break; - default: - g_assert_not_reached(); - } - - invalid_val =3D 1LL << (mxlen - 1); - - if (value =3D=3D invalid_val) { - error_setg(errp, "Unable to set marchid with MSB (%u) bit set " - "and the remaining bits zero", mxlen); - return; - } - - cpu->cfg.marchid =3D value; -} - -static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; - - visit_type_uint64(v, name, &value, errp); -} - static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2299,9 +2306,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, - cpu_set_marchid, NULL, NULL); - device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.43.0