From nobody Sat Sep 21 05:26:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705052752; cv=none; d=zohomail.com; s=zohoarc; b=kOx05lfO4cPJeXz4a7glYnkZiP63EgyY+zYu2TABAjk7M7oRZPUUl8nU0RycSzA6iIhpXaE9AQoZAMTVQQP6B1hHGrrKHadw5sAT+8LuzWVj6tm9UfnzESbZzSi6F9XC6gxbPxZOqE3OstU8TxSMtYi5bmSFGsIVtKWk5OPob0w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705052752; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=nVwcafy0HPeAHqWLdFC4FGNjTM/gr98x2iZJNwPXoD8=; b=EvtL1kORcAW4jMpwjqM8WblxQbV1tuIIxyVLtQwTPChs9v5Dcdre6SHOOCaa2V6ZmBt6R1Ejjj51hyOGH/Q0r56o5gu0ErkcTvnAQP1KkswXcTOXrpaozmn7JPShW/CnOvwTQToTWInIj9y2fLq2Mt4/xw63WtZqljMFfoyaxCY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705052752420804.587060510029; Fri, 12 Jan 2024 01:45:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rOE5T-0004eN-Mh; Fri, 12 Jan 2024 04:44:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOE5I-0004cZ-Qz; Fri, 12 Jan 2024 04:44:18 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOE5E-0005dI-5a; Fri, 12 Jan 2024 04:44:15 -0500 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 40C9hnPZ060872; Fri, 12 Jan 2024 17:43:49 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from ethan84-VirtualBox.andestech.com (10.0.12.51) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 12 Jan 2024 17:43:45 +0800 To: CC: , , , , , , , , Ethan Chen Subject: [PATCH v5 1/3] hw/core: Add config stream Date: Fri, 12 Jan 2024 17:43:33 +0800 Message-ID: <20240112094335.922010-2-ethan84@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240112094335.922010-1-ethan84@andestech.com> References: <20240112094335.922010-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.51] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 40C9hnPZ060872 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1705052753435100001 Content-Type: text/plain; charset="utf-8" Make other device can use /hw/core/stream.c by select this config. Reviewed-by: Alistair Francis Signed-off-by: Ethan Chen --- hw/Kconfig | 1 + hw/core/Kconfig | 3 +++ hw/core/meson.build | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/Kconfig b/hw/Kconfig index 9ca7b38c31..e4d153dce7 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -79,6 +79,7 @@ config XILINX config XILINX_AXI bool select PTIMER # for hw/dma/xilinx_axidma.c + select STREAM =20 config XLNX_ZYNQMP bool diff --git a/hw/core/Kconfig b/hw/core/Kconfig index 9397503656..e89ffa728b 100644 --- a/hw/core/Kconfig +++ b/hw/core/Kconfig @@ -27,3 +27,6 @@ config REGISTER =20 config SPLIT_IRQ bool + +config STREAM + bool diff --git a/hw/core/meson.build b/hw/core/meson.build index 67dad04de5..0893917b12 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -32,8 +32,8 @@ system_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files= ('platform-bus.c')) system_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c')) system_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c')) system_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c')) -system_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c')) system_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c')) +system_ss.add(when: 'CONFIG_STREAM', if_true: files('stream.c')) =20 system_ss.add(files( 'cpu-sysemu.c', --=20 2.34.1 From nobody Sat Sep 21 05:26:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705052720; cv=none; d=zohomail.com; s=zohoarc; b=dASKfNp4pUDlxxCQHumHudGVTLOHJVpDHOs04liXBVWR3s5lFasMcIHdSJUHzl4UmNyunF62HdxSccuyzUgs1tVhdaw2eY88V4xZ1JosXQb3ns2BoRT8rCubrnEcBcH/pH/AjBEuZeuus9peQQlNOM22LKB+htLNiOjtg3N/uTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705052720; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=2U0BIhocLC1Uef9FXC8dWh5T1tw4JJgpoPJlFuGUMlE=; b=mDhs7VKR6GLnYEcagYE18FLFL1WSNPMrfxnKr4ZwdDakvxtojtrVc9V/PeR2eaiPxrpHdCHSoD/h+Yl8RRN3j/H+A93TPlHauQqpZtt7m52a2O46ekKeHph7YH522zI4US3xQ6fnfJwKH1aRZ4W+7aL5/S/c5ineU2OII47PL7w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1705052720596399.62855180786596; Fri, 12 Jan 2024 01:45:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rOE5S-0004ds-RF; Fri, 12 Jan 2024 04:44:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOE5K-0004cs-Tc; Fri, 12 Jan 2024 04:44:20 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOE5F-0005dU-Hs; Fri, 12 Jan 2024 04:44:18 -0500 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 40C9hsV4060899; Fri, 12 Jan 2024 17:43:54 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from ethan84-VirtualBox.andestech.com (10.0.12.51) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 12 Jan 2024 17:43:50 +0800 To: CC: , , , , , , , , Ethan Chen Subject: [PATCH v5 2/3] Add RISC-V IOPMP support Date: Fri, 12 Jan 2024 17:43:34 +0800 Message-ID: <20240112094335.922010-3-ethan84@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240112094335.922010-1-ethan84@andestech.com> References: <20240112094335.922010-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.51] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 40C9hsV4060899 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1705052721735100001 Content-Type: text/plain; charset="utf-8" Support specification Version 1.0.0-draft4 rapid-k model. The specification url: https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specifica= tion.pdf The memory transaction from source devices connected to IOPMP will be checked by IOPMP rule. The method of connecting the source device to IOPMP as follows: For a system bus device, device connects to IOPMP by calling address_space_rw to address space iopmp_sysbus_as with MemTxAttrs.requester_id=3DSID. For a PCI bus device, device connects to IOPMP when it is on a host bridge with iopmp_setup_pci. PCI bus device has default SID from PCI BDF. IOPMP have two optional features need source device support. 1. Partially hit detection: A Source device support IOPMP partially hit detection need to send a transaction_info before transaction start and send a transaction_info with eop after transaction end. IOPMP will additionally check partially hit by transaction_info. 2. Stall: A Source device support IOPMP stall need to resend the transaction when it gets the MEMTX_IOPMP_STALL result There are three possible results of a transaction: valid, blocked, and stalled. If a transaction is valid, target address space is downstream_as(system_memory). If a transaction is blocked, it will go to blocked_io_as. The operation of blocked_io_as could be a bus error, a decode error, or it can respond a success with fabricated data depending on IOPMP ERRREACT register value. If a transaction is stalled, it will go to stall_io_as. The operation of stall_io_as does nothing but return a stall result to source device. Source device should retry the transaction if it gets a stall result. Signed-off-by: Ethan Chen --- hw/misc/Kconfig | 4 + hw/misc/meson.build | 1 + hw/misc/riscv_iopmp.c | 1130 +++++++++++++++++ hw/misc/trace-events | 4 + include/hw/misc/riscv_iopmp.h | 187 +++ .../hw/misc/riscv_iopmp_transaction_info.h | 28 + 6 files changed, 1354 insertions(+) create mode 100644 hw/misc/riscv_iopmp.c create mode 100644 include/hw/misc/riscv_iopmp.h create mode 100644 include/hw/misc/riscv_iopmp_transaction_info.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index cc8a8c1418..953569e682 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -200,4 +200,8 @@ config IOSB config XLNX_VERSAL_TRNG bool =20 +config RISCV_IOPMP + bool + select STREAM + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 36c20d5637..86b81e1690 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -35,6 +35,7 @@ system_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: file= s('sifive_e_prci.c')) system_ss.add(when: 'CONFIG_SIFIVE_E_AON', if_true: files('sifive_e_aon.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'= )) system_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.= c')) +specific_ss.add(when: 'CONFIG_RISCV_IOPMP', if_true: files('riscv_iopmp.c'= )) =20 subdir('macio') =20 diff --git a/hw/misc/riscv_iopmp.c b/hw/misc/riscv_iopmp.c new file mode 100644 index 0000000000..468863bccf --- /dev/null +++ b/hw/misc/riscv_iopmp.c @@ -0,0 +1,1130 @@ +/* + * QEMU RISC-V IOPMP (Input Output Physical Memory Protection) + * + * Copyright (c) 2023 Andes Tech. Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "trace.h" +#include "exec/exec-all.h" +#include "exec/address-spaces.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/misc/riscv_iopmp.h" +#include "memory.h" +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "trace.h" + +#define TYPE_IOPMP_IOMMU_MEMORY_REGION "iopmp-iommu-memory-region" +#define TYPE_IOPMP_TRASACTION_INFO_SINK "iopmp_transaction_info_sink" + +DECLARE_INSTANCE_CHECKER(Iopmp_StreamSink, IOPMP_TRASACTION_INFO_SINK, + TYPE_IOPMP_TRASACTION_INFO_SINK) + +#define MEMTX_IOPMP_STALL (1 << 3) + +REG32(VERSION, 0x00) + FIELD(VERSION, VENDOR, 0, 24) + FIELD(VERSION, SPECVER , 24, 8) +REG32(IMP, 0x04) + FIELD(IMP, IMPID, 0, 32) +REG32(HWCFG0, 0x08) + FIELD(HWCFG0, SID_NUM, 0, 16) + FIELD(HWCFG0, ENTRY_NUM, 16, 16) +REG32(HWCFG1, 0x0C) + FIELD(HWCFG1, MODEL, 0, 4) + FIELD(HWCFG1, TOR_EN, 4, 1) + FIELD(HWCFG1, SPS_EN, 5, 1) + FIELD(HWCFG1, USER_CFG_EN, 6, 1) + FIELD(HWCFG1, PRIENT_PROG, 7, 1) + FIELD(HWCFG1, SID_TRANSL_EN, 8, 1) + FIELD(HWCFG1, SID_TRANSL_PROG, 9, 1) + FIELD(HWCFG1, MD_NUM, 24, 7) + FIELD(HWCFG1, ENABLE, 31, 1) +REG32(HWCFG2, 0x10) + FIELD(HWCFG2, PRIO_ENTRY, 0, 16) + FIELD(HWCFG2, SID_TRANSL, 16, 16) +REG32(ENTRYOFFSET, 0x20) + FIELD(ENTRYOFFSET, OFFSET, 0, 32) +REG32(ERRREACT, 0x28) + FIELD(ERRREACT, L, 0, 1) + FIELD(ERRREACT, IE, 1, 1) + FIELD(ERRREACT, IP, 2, 1) + FIELD(ERRREACT, IRE, 4, 1) + FIELD(ERRREACT, RRE, 5, 3) + FIELD(ERRREACT, IWE, 8, 1) + FIELD(ERRREACT, RWE, 9, 3) + FIELD(ERRREACT, PEE, 28, 1) + FIELD(ERRREACT, RPE, 29, 3) +REG32(MDSTALL, 0x30) + FIELD(MDSTALL, EXEMPT, 0, 1) + FIELD(MDSTALL, MD, 1, 31) +REG32(MDSTALLH, 0x34) + FIELD(MDSTALLH, MD, 0, 32) +REG32(SIDSCP, 0x38) + FIELD(SIDSCP, SID, 0, 16) + FIELD(SIDSCP, OP, 30, 2) +REG32(MDLCK, 0x40) + FIELD(MDLCK, L, 0, 1) + FIELD(MDLCK, MD, 1, 31) +REG32(MDLCKH, 0x44) + FIELD(MDLCKH, MDH, 0, 32) +REG32(MDCFGLCK, 0x48) + FIELD(MDCFGLCK, L, 0, 1) + FIELD(MDCFGLCK, F, 1, 7) +REG32(ENTRYLCK, 0x4C) + FIELD(ENTRYLCK, L, 0, 1) + FIELD(ENTRYLCK, F, 1, 16) +REG32(ERR_REQADDR, 0x60) + FIELD(ERR_REQADDR, ADDR, 0, 32) +REG32(ERR_REQADDRH, 0x64) + FIELD(ERR_REQADDRH, ADDRH, 0, 32) +REG32(ERR_REQSID, 0x68) + FIELD(ERR_REQSID, SID, 0, 32) +REG32(ERR_REQINFO, 0x6C) + FIELD(ERR_REQINFO, NO_HIT, 0, 1) + FIELD(ERR_REQINFO, PAR_HIT, 1, 1) + FIELD(ERR_REQINFO, TYPE, 8, 3) + FIELD(ERR_REQINFO, EID, 16, 16) +REG32(MDCFG0, 0x800) + FIELD(MDCFG0, T, 0, 16) +REG32(SRCMD_EN0, 0x1000) + FIELD(SRCMD_EN0, L, 0, 1) + FIELD(SRCMD_EN0, MD, 1, 31) +REG32(SRCMD_ENH0, 0x1004) + FIELD(SRCMD_ENH0, MDH, 0, 32) +REG32(SRCMD_R0, 0x1008) + FIELD(SRCMD_R0, MD, 1, 31) +REG32(SRCMD_RH0, 0x100C) + FIELD(SRCMD_RH0, MDH, 0, 32) +REG32(SRCMD_W0, 0x1010) + FIELD(SRCMD_W0, MD, 1, 31) +REG32(SRCMD_WH0, 0x1014) + FIELD(SRCMD_WH0, MDH, 0, 32) +REG32(ENTRY_ADDR0, 0x4000) + FIELD(ENTRY_ADDR0, ADDR, 0, 32) +REG32(ENTRY_ADDRH0, 0x4004) + FIELD(ENTRY_ADDRH0, ADDRH, 0, 32) +REG32(ENTRY_CFG0, 0x4008) + FIELD(ENTRY_CFG0, R, 0, 1) + FIELD(ENTRY_CFG0, W, 1, 1) + FIELD(ENTRY_CFG0, X, 2, 1) + FIELD(ENTRY_CFG0, A, 3, 2) +REG32(ENTRY_USER_CFG0, 0x400C) + FIELD(ENTRY_USER_CFG0, IM, 0, 32) + +static void iopmp_decode_napot(uint64_t a, uint64_t *sa, + uint64_t *ea) +{ + /* + * aaaa...aaa0 8-byte NAPOT range + * aaaa...aa01 16-byte NAPOT range + * aaaa...a011 32-byte NAPOT range + * ... + * aa01...1111 2^XLEN-byte NAPOT range + * a011...1111 2^(XLEN+1)-byte NAPOT range + * 0111...1111 2^(XLEN+2)-byte NAPOT range + * 1111...1111 Reserved + */ + + a =3D (a << 2) | 0x3; + *sa =3D a & (a + 1); + *ea =3D a | (a + 1); +} + +static void iopmp_update_rule(IopmpState *s, uint32_t entry_index) +{ + uint8_t this_cfg =3D s->regs.entry[entry_index].cfg_reg; + uint64_t this_addr =3D s->regs.entry[entry_index].addr_reg | + ((uint64_t)s->regs.entry[entry_index].addrh_reg <= < 32); + uint64_t prev_addr =3D 0u; + uint64_t sa =3D 0u; + uint64_t ea =3D 0u; + + if (entry_index >=3D 1u) { + prev_addr =3D s->regs.entry[entry_index - 1].addr_reg | + ((uint64_t)s->regs.entry[entry_index - 1].addrh_reg <<= 32); + } + + switch (FIELD_EX32(this_cfg, ENTRY_CFG0, A)) { + case IOPMP_AMATCH_OFF: + sa =3D 0u; + ea =3D -1; + break; + + case IOPMP_AMATCH_TOR: + sa =3D (prev_addr) << 2; /* shift up from [xx:0] to [xx+2:2] */ + ea =3D ((this_addr) << 2) - 1u; + if (sa > ea) { + sa =3D ea =3D 0u; + } + break; + + case IOPMP_AMATCH_NA4: + sa =3D this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ + ea =3D (sa + 4u) - 1u; + break; + + case IOPMP_AMATCH_NAPOT: + iopmp_decode_napot(this_addr, &sa, &ea); + break; + + default: + sa =3D 0u; + ea =3D 0u; + break; + } + + s->entry_addr[entry_index].sa =3D sa; + s->entry_addr[entry_index].ea =3D ea; +} + +static uint64_t iopmp_read(void *opaque, hwaddr addr, unsigned size) +{ + IopmpState *s =3D IOPMP(opaque); + uint32_t rz =3D 0; + uint32_t sid; + switch (addr) { + case A_VERSION ... A_ENTRY_USER_CFG0 + 16 * (IOPMP_MAX_ENTRY_NUM - 1): + switch (addr) { + case A_VERSION: + rz =3D VENDER_VIRT << R_VERSION_VENDOR_SHIFT | + SPECVER_1_0_0_DRAFT4 << R_VERSION_SPECVER_SHIFT; + break; + case A_IMP: + rz =3D IMPID_1_0_0_DRAFT4_0; + break; + case A_HWCFG0: + rz =3D s->sid_num << R_HWCFG0_SID_NUM_SHIFT | + s->entry_num << R_HWCFG0_ENTRY_NUM_SHIFT; + break; + case A_HWCFG1: + rz =3D s->model << R_HWCFG1_MODEL_SHIFT | + CFG_TOR_EN << R_HWCFG1_TOR_EN_SHIFT | + s->sps_en << R_HWCFG1_SPS_EN_SHIFT | + CFG_USER_CFG_EN << R_HWCFG1_USER_CFG_EN_SHIFT | + s->prient_prog << R_HWCFG1_PRIENT_PROG_SHIFT | + s->sid_transl_en << R_HWCFG1_SID_TRANSL_EN_SHIFT | + s->sid_transl_prog << R_HWCFG1_SID_TRANSL_PROG_SHIFT | + s->md_num << R_HWCFG1_MD_NUM_SHIFT | + s->enable << R_HWCFG1_ENABLE_SHIFT ; + break; + case A_HWCFG2: + rz =3D s->prio_entry << R_HWCFG2_PRIO_ENTRY_SHIFT | + s->sid_transl << R_HWCFG2_SID_TRANSL_SHIFT; + break; + case A_ENTRYOFFSET: + rz =3D A_ENTRY_ADDR0; + break; + case A_ERRREACT: + rz =3D s->regs.errreact; + break; + case A_MDSTALL: + rz =3D s->regs.mdstall; + break; + case A_MDSTALLH: + rz =3D s->regs.mdstallh; + break; + case A_SIDSCP: + sid =3D FIELD_EX32(s->regs.sidscp, SIDSCP, SID); + if (sid < s->sid_num) { + rz =3D sid | (s->sidscp_op[sid]) << R_SIDSCP_OP_SHIFT; + } else { + rz =3D sid | 3 << R_SIDSCP_OP_SHIFT; + } + break; + case A_MDLCK: + rz =3D s->regs.mdlck; + break; + case A_MDLCKH: + rz =3D s->regs.mdlckh; + break; + case A_MDCFGLCK: + rz =3D s->regs.mdcfglck; + break; + case A_ENTRYLCK: + rz =3D s->regs.entrylck; + break; + case A_ERR_REQADDR: + rz =3D s->regs.err_reqaddr & UINT32_MAX; + break; + case A_ERR_REQADDRH: + rz =3D s->regs.err_reqaddr >> 32; + break; + case A_ERR_REQSID: + rz =3D s->regs.err_reqsid; + break; + case A_ERR_REQINFO: + rz =3D s->regs.err_reqinfo; + break; + + default: + if (addr >=3D A_MDCFG0 && + addr < A_MDCFG0 + 4 * (s->md_num - 1)) { + int offset =3D addr - A_MDCFG0; + int idx =3D offset >> 2; + if (idx =3D=3D 0) { + if (offset =3D=3D 0) { + rz =3D s->regs.mdcfg[idx]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + } else { + /* Only MDCFG0 is implemented in rapid-k model*/ + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + } else if (addr >=3D A_SRCMD_EN0 && + addr < A_SRCMD_WH0 + 32 * (s->sid_num - 1)) { + int offset =3D addr - A_SRCMD_EN0; + int idx =3D offset >> 5; + offset &=3D 0x1f; + if (offset =3D=3D 0) { + rz =3D s->regs.srcmd_en[idx]; + } else if (offset =3D=3D 4) { + rz =3D s->regs.srcmd_enh[idx]; + } else if (offset =3D=3D 8) { + rz =3D s->regs.srcmd_r[idx]; + } else if (offset =3D=3D 12) { + rz =3D s->regs.srcmd_rh[idx]; + } else if (offset =3D=3D 16) { + rz =3D s->regs.srcmd_w[idx]; + } else if (offset =3D=3D 24) { + rz =3D s->regs.srcmd_wh[idx]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + } else if (addr >=3D A_ENTRY_ADDR0 && + addr < A_ENTRY_USER_CFG0 + 16 * (s->entry_num - 1))= { + int offset =3D addr - A_ENTRY_ADDR0; + int idx =3D offset >> 4; + offset &=3D 0xf; + if (offset =3D=3D 0) { + rz =3D s->regs.entry[idx].addr_reg; + } else if (offset =3D=3D 4) { + rz =3D s->regs.entry[idx].addrh_reg; + } else if (offset =3D=3D 8) { + rz =3D s->regs.entry[idx].cfg_reg; + } else if (offset =3D=3D 12) { + /* Does not support user customized permission */ + rz =3D 0; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + break; + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + trace_iopmp_read(addr, rz); + return rz; +} + +static void +iopmp_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) +{ + IopmpState *s =3D IOPMP(opaque); + int value_f; + int reg_f; + uint32_t sid, op; + uint32_t value32 =3D value; + trace_iopmp_write(addr, value32); + + switch (addr) { + case A_VERSION ... A_ENTRY_USER_CFG0 + 16 * (IOPMP_MAX_ENTRY_NUM - 1): + switch (addr) { + case A_VERSION: /* RO */ + break; + case A_IMP: /* RO */ + break; + case A_HWCFG0: /* RO */ + break; + case A_HWCFG1: + if (FIELD_EX32(value32, HWCFG1, PRIENT_PROG)) { + /* W1C */ + s->prient_prog =3D 0; + } + if (FIELD_EX32(value32, HWCFG1, SID_TRANSL_PROG)) { + /* W1C */ + s->sid_transl_prog =3D 0; + } + if (FIELD_EX32(value32, HWCFG1, ENABLE)) { + /* W1S */ + s->enable =3D 1; + } + break; + case A_HWCFG2: + if (s->prient_prog) { + s->prio_entry =3D FIELD_EX32(value32, HWCFG2, PRIO_ENTRY); + } + if (s->sid_transl_en && s->sid_transl_prog) { + s->sid_transl =3D FIELD_EX32(value32, HWCFG2, SID_TRANSL); + } + break; + case A_ERRREACT: + if (!FIELD_EX32(s->regs.errreact, ERRREACT, L)) { + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRR= EACT, L, + FIELD_EX32(value32, ERRREACT, L)); + if (FIELD_EX32(value32, ERRREACT, IP)) { + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRR= EACT, + IP, 0); + } + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , IE, + FIELD_EX32(value32, ERRREACT, IE)); + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , IRE, + FIELD_EX32(value32, ERRREACT, IRE)= ); + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , RRE, + FIELD_EX32(value32, ERRREACT, RRE)= ); + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , IWE, + FIELD_EX32(value32, ERRREACT, IWE)= ); + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , RWE, + FIELD_EX32(value32, ERRREACT, RWE)= ); + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , PEE, + FIELD_EX32(value32, ERRREACT, PEE)= ); + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT= , RPE, + FIELD_EX32(value32, ERRREACT, RPE)= ); + } else { + if (FIELD_EX32(value32, ERRREACT, IP)) { + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRR= EACT, + IP, 0); + } + } + break; + case A_MDSTALL: + s->regs.mdstall =3D value32; + break; + case A_MDSTALLH: + s->regs.mdstallh =3D value32; + break; + case A_SIDSCP: + sid =3D FIELD_EX32(value32, SIDSCP, SID); + op =3D FIELD_EX32(value32, SIDSCP, OP); + if (sid < s->sid_num) { + if (op !=3D SIDSCP_OP_QUERY) { + s->sidscp_op[sid] =3D op; + s->regs.sidscp =3D value32; + } + } else { + s->regs.sidscp =3D sid | (0x3 << R_SIDSCP_OP_SHIFT); + } + break; + case A_MDLCK: + if (!FIELD_EX32(s->regs.mdlck, MDLCK, L)) { + s->regs.mdlck =3D value32; + } + break; + case A_MDLCKH: + if (!FIELD_EX32(s->regs.mdlck, MDLCK, L)) { + s->regs.mdlckh =3D value32; + } + break; + case A_MDCFGLCK: + if (!FIELD_EX32(s->regs.mdcfglck, MDCFGLCK, L)) { + value_f =3D FIELD_EX32(value32, MDCFGLCK, F); + reg_f =3D FIELD_EX32(s->regs.mdcfglck, MDCFGLCK, F); + if (value_f > reg_f) { + s->regs.mdcfglck =3D FIELD_DP32(s->regs.mdcfglck, MDCF= GLCK, F, + value_f); + } + s->regs.mdcfglck =3D FIELD_DP32(s->regs.mdcfglck, MDCFGLCK= , L, + FIELD_EX32(value32, MDCFGLCK, L)); + } + break; + case A_ENTRYLCK: + if (!(FIELD_EX32(s->regs.entrylck, ENTRYLCK, L))) { + value_f =3D FIELD_EX32(value32, ENTRYLCK, F); + reg_f =3D FIELD_EX32(s->regs.entrylck, ENTRYLCK, F); + if (value_f > reg_f) { + s->regs.entrylck =3D FIELD_DP32(s->regs.entrylck, ENTR= YLCK, F, + value_f); + } + s->regs.entrylck =3D FIELD_DP32(s->regs.entrylck, ENTRYLCK= , F, + FIELD_EX32(value32, ENTRYLCK, F)); + } + case A_ERR_REQADDR: /* RO */ + break; + case A_ERR_REQADDRH: /* RO */ + break; + case A_ERR_REQSID: /* RO */ + break; + case A_ERR_REQINFO: /* RO */ + break; + + default: + if (addr >=3D A_MDCFG0 && + addr < A_MDCFG0 + 4 * (s->md_num - 1)) { + int offset =3D addr - A_MDCFG0; + int idx =3D offset >> 2; + /* RO in rapid-k model */ + if (idx > 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + } else if (addr >=3D A_SRCMD_EN0 && + addr < A_SRCMD_WH0 + 32 * (s->sid_num - 1)) { + int offset =3D addr - A_SRCMD_EN0; + int idx =3D offset >> 5; + offset &=3D 0x1f; + if (offset % 4) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } else if (FIELD_EX32(s->regs.srcmd_en[idx], SRCMD_EN0, L) + =3D=3D 0) { + if (offset =3D=3D 0) { + s->regs.srcmd_en[idx] =3D + FIELD_DP32(s->regs.srcmd_en[idx], SRCMD_EN= 0, MD, + FIELD_EX32(value32, SRCMD_EN0, = MD)); + s->regs.srcmd_en[idx] =3D + FIELD_DP32(s->regs.srcmd_en[idx], SRCMD_EN0, L, + FIELD_EX32(value32, SRCMD_EN0, L)); + } else if (offset =3D=3D 4) { + s->regs.srcmd_enh[idx] =3D + FIELD_DP32(s->regs.srcmd_enh[idx], SRCMD_ENH0,= MDH, + value32); + } else if (offset =3D=3D 8 && s->sps_en) { + s->regs.srcmd_r[idx] =3D + FIELD_DP32(s->regs.srcmd_r[idx], SRCMD_R0, MD, + FIELD_EX32(value32, SRCMD_R0, MD)); + } else if (offset =3D=3D 12 && s->sps_en) { + s->regs.srcmd_rh[idx] =3D + FIELD_DP32(s->regs.srcmd_rh[idx], SRCMD_RH0, M= DH, + value32); + } else if (offset =3D=3D 16 && s->sps_en) { + s->regs.srcmd_w[idx] =3D + FIELD_DP32(s->regs.srcmd_w[idx], SRCMD_W0, MD, + FIELD_EX32(value32, SRCMD_W0, MD)); + } else if (offset =3D=3D 24 && s->sps_en) { + s->regs.srcmd_wh[idx] =3D + FIELD_DP32(s->regs.srcmd_wh[idx], SRCMD_WH0, M= DH, + value32); + } + } + } else if (addr >=3D A_ENTRY_ADDR0 && + addr < A_ENTRY_USER_CFG0 + 16 * (s->entry_num - 1))= { + int offset =3D addr - A_ENTRY_ADDR0; + int idx =3D offset >> 4; + offset &=3D 0xf; + if (offset =3D=3D 0) { + s->regs.entry[idx].addr_reg =3D value32; + } else if (offset =3D=3D 4) { + s->regs.entry[idx].addrh_reg =3D value32; + } else if (offset =3D=3D 8) { + s->regs.entry[idx].cfg_reg =3D value32; + } else if (offset =3D=3D 12) { + /* Does not support user customized permission */ + ; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", + __func__, (int)addr); + } + iopmp_update_rule(s, idx); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", __func= __, + (int)addr); + } + /* If IOPMP permission of any addr has been changed, */ + /* flush TLB pages. */ + tlb_flush_all_cpus_synced(current_cpu); + break; + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad addr %x\n", __func__, + (int)addr); + } +} + +/* Match entry in memory domain */ +static int match_entry_md(IopmpState *s, int md_idx, hwaddr s_addr, + hwaddr e_addr, int *entry_idx) +{ + int entry_idx_s, entry_idx_e; + int result =3D ENTRY_NO_HIT; + int i =3D 0; + entry_idx_s =3D md_idx * s->regs.mdcfg[0]; + entry_idx_e =3D (md_idx + 1) * s->regs.mdcfg[0]; + if (entry_idx_s >=3D s->entry_num) { + return result; + } + if (entry_idx_e > s->entry_num) { + entry_idx_e =3D s->entry_num; + } + i =3D entry_idx_s; + while (i < entry_idx_e) { + if (s_addr >=3D s->entry_addr[i].sa && s_addr <=3D s->entry_addr[i= ].ea) { + /* check end address */ + if (e_addr >=3D s->entry_addr[i].sa && + e_addr <=3D s->entry_addr[i].ea) { + *entry_idx =3D i; + return ENTRY_HIT; + } else if (i >=3D s->prio_entry) { + /* record result and continue for non-prio_entry */ + result =3D ENTRY_PAR_HIT; + continue; + } else { + return ENTRY_PAR_HIT; + } + } + i++; + } + return result; +} + +static int match_entry(IopmpState *s, int sid, hwaddr s_addr, hwaddr e_add= r, + int *match_md_idx, int *match_entry_idx) +{ + int cur_result =3D ENTRY_NO_HIT; + int result =3D ENTRY_NO_HIT; + /* Remove lock bit */ + uint64_t srcmd_en =3D ((uint64_t)s->regs.srcmd_en[sid] | + ((uint64_t)s->regs.srcmd_enh[sid] << 32)) >> 1; + + for (int md_idx =3D 0; md_idx < s->md_num; md_idx++) { + if (srcmd_en & (1ULL << md_idx)) { + cur_result =3D match_entry_md(s, md_idx, s_addr, e_addr, + match_entry_idx); + if (cur_result =3D=3D ENTRY_HIT) { + *match_md_idx =3D md_idx; + return cur_result; + } + if (cur_result > result) { + result =3D cur_result; + } + } + } + return result; +} + +static bool check_md_stall(IopmpState *s, int md_idx) +{ + uint64_t mdstall =3D s->regs.mdstall | (uint64_t)s->regs.mdstallh << 3= 2; + uint64_t md_selected =3D mdstall & (1 << (md_idx + R_MDSTALL_EXEMPT_SH= IFT)); + if (FIELD_EX32(s->regs.mdstall, MDSTALL, EXEMPT)) { + return !md_selected; + } else { + return md_selected; + } +} + +static inline bool check_sidscp_stall(IopmpState *s, int sid) +{ + return s->sidscp_op[sid] =3D=3D SIDSCP_OP_STALL; +} + +static void iopmp_error_reaction(IopmpState *s, uint32_t id, hwaddr start, + hwaddr end, uint32_t info) +{ + if (start =3D=3D s->prev_error_info[id].start_addr && + end =3D=3D s->prev_error_info[id].end_addr && + info =3D=3D s->prev_error_info[id].reqinfo) { + /* skip following error */ + ; + } else { + s->prev_error_info[id].start_addr =3D start; + s->prev_error_info[id].end_addr =3D end; + s->prev_error_info[id].reqinfo =3D info; + if (!FIELD_EX32(s->regs.errreact, ERRREACT, IP)) { + s->regs.errreact =3D FIELD_DP32(s->regs.errreact, ERRREACT, IP= , 1); + s->regs.err_reqsid =3D id; + s->regs.err_reqaddr =3D start; + s->regs.err_reqinfo =3D info; + + if (FIELD_EX32(info, ERR_REQINFO, TYPE) =3D=3D ERR_REQINFO_TYP= E_READ + && FIELD_EX32(s->regs.errreact, ERRREACT, IE) && + FIELD_EX32(s->regs.errreact, ERRREACT, IRE)) { + qemu_set_irq(s->irq, 1); + } + if (FIELD_EX32(info, ERR_REQINFO, TYPE) =3D=3D ERR_REQINFO_TYP= E_WRITE && + FIELD_EX32(s->regs.errreact, ERRREACT, IE) && + FIELD_EX32(s->regs.errreact, ERRREACT, IWE)) { + qemu_set_irq(s->irq, 1); + } + } + } +} + +static IOMMUTLBEntry iopmp_translate(IOMMUMemoryRegion *iommu, hwaddr addr, + IOMMUAccessFlags flags, int iommu_idx) +{ + bool is_stalled =3D false; + int pci_id =3D 0; + int sid =3D iommu_idx; + IopmpState *s; + MemoryRegion *mr =3D MEMORY_REGION(iommu); + + /* Find IOPMP of iommu */ + if (strncmp(mr->name, "riscv-iopmp-sysbus-iommu", 24) !=3D 0) { + sscanf(mr->name, "riscv-iopmp-pci-iommu%d", &pci_id); + iopmp_pci_addressspcace *pci_s =3D container_of(iommu, + iopmp_pci_addressspc= ace, + iommu); + s =3D IOPMP(pci_s->iopmp); + /* If device does not specify sid, use id from pci */ + if (sid =3D=3D 0) { + sid =3D pci_id; + } + } else { + s =3D IOPMP(container_of(iommu, IopmpState, iommu)); + } + + hwaddr start_addr, end_addr; + if (s->transaction_state[sid].supported) { + /* get transaction_state if device supported */ + start_addr =3D s->transaction_state[sid].start_addr; + end_addr =3D s->transaction_state[sid].end_addr; + if (addr > end_addr || addr < start_addr || + !s->transaction_state[sid].running) { + qemu_log_mask(LOG_GUEST_ERROR, "transaction_state error."); + } + } else { + start_addr =3D addr; + end_addr =3D addr; + } + + IOMMUTLBEntry entry =3D { + .target_as =3D &s->downstream_as, + .iova =3D addr, + .translated_addr =3D addr, + .addr_mask =3D (~(hwaddr)0), + .perm =3D IOMMU_NONE, + }; + + if (!s->enable) { + /* Bypass IOPMP */ + entry.perm =3D IOMMU_RW; + return entry; + } + + int entry_idx =3D -1; + int md_idx =3D -1; + int result =3D match_entry(s, sid, start_addr, end_addr, &md_idx, &ent= ry_idx); + int srcmd_rw; + uint32_t error_info =3D 0; + if (result =3D=3D ENTRY_HIT) { + is_stalled =3D check_md_stall(s, md_idx) || check_sidscp_stall(s, = sid); + if (is_stalled) { + entry.target_as =3D &s->stall_io_as; + entry.perm =3D IOMMU_RW; + return entry; + } + entry.perm =3D s->regs.entry[entry_idx].cfg_reg & 0x7; + if (s->sps_en) { + /* SPS extension does not affect x permission */ + if (md_idx <=3D 31) { + srcmd_rw =3D 0x4 | ((s->regs.srcmd_r[sid] >> + (md_idx + R_SRCMD_R0_MD_SHIFT)) & 0x1); + srcmd_rw |=3D ((s->regs.srcmd_w[sid] >> + (md_idx + R_SRCMD_W0_MD_SHIFT)) & 0x1) << 1; + } else { + srcmd_rw =3D 0x4 | ((s->regs.srcmd_rh[sid] >> + (md_idx + R_SRCMD_R0_MD_SHIFT - 32)) & 0= x1); + srcmd_rw |=3D ((s->regs.srcmd_wh[sid] >> + (md_idx + R_SRCMD_W0_MD_SHIFT - 32)) & 0x1) <= < 1; + } + entry.perm &=3D srcmd_rw; + } + if ((entry.perm & flags) =3D=3D 0) { + /* permission denied */ + error_info =3D FIELD_DP32(error_info, ERR_REQINFO, EID, entry_= idx); + error_info =3D FIELD_DP32(error_info, ERR_REQINFO, TYPE, (flag= s - 1)); + iopmp_error_reaction(s, sid, start_addr, end_addr, error_info); + entry.target_as =3D &s->blocked_io_as; + entry.perm =3D IOMMU_RW; + } else { + entry.addr_mask =3D s->entry_addr[entry_idx].ea - + s->entry_addr[entry_idx].sa; + /* clear error info */ + s->prev_error_info[sid].reqinfo =3D 0; + if (s->sid_transl_en) { + /* pass to next iopmp */ + if (s->next_iommu) { + int new_sid =3D s->sid_transl; + IopmpState *next_s =3D IOPMP(container_of(s->next_iomm= u, + IopmpState, io= mmu)); + next_s->transaction_state[new_sid].supported =3D true; + while (next_s->transaction_state[new_sid].running) { + ; + } + /* Send transcation info to next IOPMP */ + qemu_mutex_lock(&next_s->iopmp_transaction_mutex); + next_s->transaction_state[new_sid].running =3D 1; + qemu_mutex_unlock(&next_s->iopmp_transaction_mutex); + next_s->transaction_state[new_sid].start_addr =3D star= t_addr; + next_s->transaction_state[new_sid].end_addr =3D end_ad= dr; + /* Get result from next IOPMP */ + entry =3D iopmp_translate(s->next_iommu, addr, flags, + s->sid_transl); + + /* Finish the transcation */ + qemu_mutex_lock(&next_s->iopmp_transaction_mutex); + next_s->transaction_state[new_sid].running =3D 0; + qemu_mutex_unlock(&next_s->iopmp_transaction_mutex); + + return entry; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "Next iopmp is not foun= d."); + } + } + } + } else { + if (result =3D=3D ENTRY_PAR_HIT) { + error_info =3D FIELD_DP32(error_info, ERR_REQINFO, PAR_HIT, 1); + error_info =3D FIELD_DP32(error_info, ERR_REQINFO, TYPE, (flag= s - 1)); + iopmp_error_reaction(s, sid, start_addr, end_addr, error_info); + } else { + error_info =3D FIELD_DP32(error_info, ERR_REQINFO, NO_HIT, 1); + error_info =3D FIELD_DP32(error_info, ERR_REQINFO, TYPE, (flag= s - 1)); + iopmp_error_reaction(s, sid, start_addr, end_addr, error_info); + } + entry.target_as =3D &s->blocked_io_as; + entry.perm =3D IOMMU_RW; + } + return entry; +} + +static const MemoryRegionOps iopmp_ops =3D { + .read =3D iopmp_read, + .write =3D iopmp_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D {.min_access_size =3D 4, .max_access_size =3D 4} +}; + +static MemTxResult iopmp_block_write(void *opaque, hwaddr addr, uint64_t v= alue, + unsigned size, MemTxAttrs attrs) +{ + IopmpState *s =3D IOPMP(opaque); + + switch (FIELD_EX32(s->regs.errreact, ERRREACT, RWE)) { + case RWE_BUS_ERROR: + return MEMTX_ERROR; + break; + case RWE_DECODE_ERROR: + return MEMTX_DECODE_ERROR; + break; + case RWE_SUCCESS: + return MEMTX_OK; + break; + default: + break; + } + return MEMTX_OK; +} + +static MemTxResult iopmp_block_read(void *opaque, hwaddr addr, uint64_t *p= data, + unsigned size, MemTxAttrs attrs) +{ + IopmpState *s =3D IOPMP(opaque); + + switch (FIELD_EX32(s->regs.errreact, ERRREACT, RRE)) { + case RRE_BUS_ERROR: + return MEMTX_ERROR; + break; + case RRE_DECODE_ERROR: + return MEMTX_DECODE_ERROR; + break; + case RRE_SUCCESS_ZEROS: + *pdata =3D 0; + return MEMTX_OK; + break; + case RRE_SUCCESS_ONES: + *pdata =3D UINT64_MAX; + return MEMTX_OK; + break; + default: + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps iopmp_block_io_ops =3D { + .read_with_attrs =3D iopmp_block_read, + .write_with_attrs =3D iopmp_block_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D {.min_access_size =3D 1, .max_access_size =3D 8}, +}; + +static MemTxResult iopmp_handle_stall(IopmpState *s, hwaddr addr, + MemTxAttrs attrs) +{ + return MEMTX_IOPMP_STALL; +} + +static MemTxResult iopmp_stall_write(void *opaque, hwaddr addr, uint64_t v= alue, + unsigned size, MemTxAttrs attrs) +{ + IopmpState *s =3D IOPMP(opaque); + + return iopmp_handle_stall(s, addr, attrs); +} + +static MemTxResult iopmp_stall_read(void *opaque, hwaddr addr, uint64_t *p= data, + unsigned size, MemTxAttrs attrs) +{ + IopmpState *s =3D IOPMP(opaque); + + *pdata =3D 0; + return iopmp_handle_stall(s, addr, attrs); +} + +static const MemoryRegionOps iopmp_stall_io_ops =3D { + .read_with_attrs =3D iopmp_stall_read, + .write_with_attrs =3D iopmp_stall_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D {.min_access_size =3D 1, .max_access_size =3D 8}, +}; + +static void iopmp_realize(DeviceState *dev, Error **errp) +{ + Object *obj =3D OBJECT(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + IopmpState *s =3D IOPMP(dev); + s->downstream =3D get_system_memory(); + uint64_t size =3D memory_region_size(s->downstream); + + qemu_mutex_init(&s->iopmp_transaction_mutex); + s->prient_prog =3D 1; + s->sid_num =3D MIN(s->sid_num, IOPMP_MAX_SID_NUM); + s->md_num =3D MIN(s->md_num, IOPMP_MAX_MD_NUM); + s->entry_num =3D MIN(s->entry_num, IOPMP_MAX_ENTRY_NUM); + if (s->sid_transl_en) { + s->sid_transl_prog =3D 1; + } + if (!s->model_str || strcmp(s->model_str, "rapidk") =3D=3D 0) { + /* apply default model */ + s->model =3D IOPMP_MODEL_RAPIDK; + s->regs.mdcfglck =3D FIELD_DP32(s->regs.mdcfglck, MDCFGLCK, F, s->= md_num); + s->regs.mdcfglck =3D FIELD_DP32(s->regs.mdcfglck, MDCFGLCK, L, 1); + s->regs.mdcfg[0] =3D s->k; + } else { + qemu_log_mask(LOG_UNIMP, "IOPMP model %s is not supported. " + "Vailid values is rapidk.", s->model_str); + } + memory_region_init_iommu(&s->iommu, sizeof(s->iommu), + TYPE_IOPMP_IOMMU_MEMORY_REGION, + obj, "riscv-iopmp-sysbus-iommu", UINT64_MAX); + address_space_init(&s->iopmp_sysbus_as, MEMORY_REGION(&s->iommu), "iom= mu"); + memory_region_init_io(&s->mmio, obj, &iopmp_ops, + s, "iopmp-regs", 0x100000); + sysbus_init_mmio(sbd, &s->mmio); + memory_region_init_io(&s->blocked_io, obj, &iopmp_block_io_ops, + s, "iopmp-blocked-io", size); + address_space_init(&s->downstream_as, s->downstream, + "iopmp-downstream-as"); + address_space_init(&s->blocked_io_as, &s->blocked_io, + "iopmp-blocked-io-as"); + + memory_region_init_io(&s->stall_io, obj, &iopmp_stall_io_ops, + s, "iopmp-stall-io", size); + address_space_init(&s->stall_io_as, &s->stall_io, + "iopmp-stall-io-as"); + + object_initialize_child(OBJECT(s), "iopmp_transaction_info", + &s->transaction_info_sink, + TYPE_IOPMP_TRASACTION_INFO_SINK); +} + +static void iopmp_reset(DeviceState *dev) +{ + IopmpState *s =3D IOPMP(dev); + qemu_set_irq(s->irq, 0); + memset(&s->regs, 0, sizeof(iopmp_regs)); + memset(&s->entry_addr, 0, IOPMP_MAX_ENTRY_NUM * sizeof(iopmp_addr_t)); + memset(&s->prev_error_info, 0, + IOPMP_MAX_SID_NUM * sizeof(iopmp_error_info)); + + if (s->model =3D=3D IOPMP_MODEL_RAPIDK) { + s->regs.mdcfglck =3D FIELD_DP32(s->regs.mdcfglck, MDCFGLCK, F, s->= md_num); + s->regs.mdcfglck =3D FIELD_DP32(s->regs.mdcfglck, MDCFGLCK, L, 1); + s->regs.mdcfg[0] =3D s->k; + } + s->regs.errreact =3D 0; + + s->prient_prog =3D 1; + if (s->sid_transl_en) { + s->sid_transl_prog =3D 1; + } +} + +static int iopmp_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs) +{ + unsigned int sid =3D attrs.requester_id; + return sid; +} + +static void iopmp_iommu_memory_region_class_init(ObjectClass *klass, void = *data) +{ + IOMMUMemoryRegionClass *imrc =3D IOMMU_MEMORY_REGION_CLASS(klass); + + imrc->translate =3D iopmp_translate; + imrc->attrs_to_index =3D iopmp_attrs_to_index; +} + +static Property iopmp_property[] =3D { + DEFINE_PROP_STRING("model", IopmpState, model_str), + DEFINE_PROP_BOOL("sps_en", IopmpState, sps_en, false), + DEFINE_PROP_BOOL("sid_transl_en", IopmpState, sid_transl_en, false), + DEFINE_PROP_UINT32("k", IopmpState, k, CFG_IOPMP_MODEL_K), + DEFINE_PROP_UINT32("prio_entry", IopmpState, prio_entry, CFG_PRIO_ENTR= Y), + DEFINE_PROP_UINT32("sid_num", IopmpState, sid_num, IOPMP_MAX_SID_NUM), + DEFINE_PROP_UINT32("md_num", IopmpState, md_num, IOPMP_MAX_MD_NUM), + DEFINE_PROP_UINT32("entry_num", IopmpState, entry_num, IOPMP_MAX_ENTRY= _NUM), + DEFINE_PROP_END_OF_LIST(), +}; + +static void iopmp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + device_class_set_props(dc, iopmp_property); + dc->realize =3D iopmp_realize; + dc->reset =3D iopmp_reset; +} + +static void iopmp_init(Object *obj) +{ + IopmpState *s =3D IOPMP(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + sysbus_init_irq(sbd, &s->irq); +} + +static const TypeInfo iopmp_info =3D { + .name =3D TYPE_IOPMP, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IopmpState), + .instance_init =3D iopmp_init, + .class_init =3D iopmp_class_init, +}; + +static const TypeInfo +iopmp_iommu_memory_region_info =3D { + .name =3D TYPE_IOPMP_IOMMU_MEMORY_REGION, + .parent =3D TYPE_IOMMU_MEMORY_REGION, + .class_init =3D iopmp_iommu_memory_region_class_init, +}; + + +void +cascade_iopmp(DeviceState *cur_dev, DeviceState *next_dev) +{ + IopmpState *s =3D IOPMP(cur_dev); + s->sid_transl_en =3D true; + IopmpState *next_s =3D IOPMP(next_dev); + s->next_iommu =3D &next_s->iommu; +} + +static AddressSpace *iopmp_find_add_as(PCIBus *bus, void *opaque, int devf= n) +{ + IopmpState *s =3D opaque; + uint32_t id =3D PCI_BUILD_BDF(pci_bus_num(bus), devfn) % s->sid_num; + iopmp_pci_addressspcace *iopmp_pci =3D s->iopmp_pci[id]; + if (iopmp_pci =3D=3D NULL) { + char name[64]; + snprintf(name, sizeof(name), "riscv-iopmp-pci-iommu%d", id); + iopmp_pci =3D g_new0(iopmp_pci_addressspcace, 1); + iopmp_pci->iopmp =3D opaque; + memory_region_init_iommu(&iopmp_pci->iommu, + sizeof(iopmp_pci->iommu), + TYPE_IOPMP_IOMMU_MEMORY_REGION, + OBJECT(s), name, UINT64_MAX); + address_space_init(&iopmp_pci->as, + MEMORY_REGION(&iopmp_pci->iommu), "iommu"); + } + return &iopmp_pci->as; +} + +static const PCIIOMMUOps iopmp_iommu_ops =3D { + .get_address_space =3D iopmp_find_add_as, +}; + +void iopmp_setup_pci(DeviceState *iopmp_dev, PCIBus *bus) +{ + IopmpState *s =3D IOPMP(iopmp_dev); + pci_setup_iommu(bus, &iopmp_iommu_ops, s); +} + +static size_t +transaction_info_push(StreamSink *transaction_info_sink, unsigned char *bu= f, + size_t len, bool eop) +{ + Iopmp_StreamSink *ss =3D IOPMP_TRASACTION_INFO_SINK(transaction_info_s= ink); + IopmpState *s =3D IOPMP(container_of(ss, IopmpState, + transaction_info_sink)); + iopmp_transaction_info signal; + memcpy(&signal, buf, len); + uint32_t sid =3D signal.sid; + + if (s->transaction_state[sid].running) { + if (eop) { + /* Finish the transaction */ + qemu_mutex_lock(&s->iopmp_transaction_mutex); + s->transaction_state[sid].running =3D 0; + qemu_mutex_unlock(&s->iopmp_transaction_mutex); + return 1; + } else { + /* Transaction is already running */ + return 0; + } + } else if (len =3D=3D sizeof(iopmp_transaction_info)) { + /* Get the transaction info */ + s->transaction_state[sid].supported =3D 1; + qemu_mutex_lock(&s->iopmp_transaction_mutex); + s->transaction_state[sid].running =3D 1; + qemu_mutex_unlock(&s->iopmp_transaction_mutex); + + s->transaction_state[sid].start_addr =3D signal.start_addr; + s->transaction_state[sid].end_addr =3D signal.end_addr; + return 1; + } + return 0; +} + +static void iopmp_transaction_info_sink_class_init(ObjectClass *klass, + void *data) +{ + StreamSinkClass *ssc =3D STREAM_SINK_CLASS(klass); + ssc->push =3D transaction_info_push; +} + +static const TypeInfo transaction_info_sink =3D { + .name =3D TYPE_IOPMP_TRASACTION_INFO_SINK, + .parent =3D TYPE_OBJECT, + .instance_size =3D sizeof(Iopmp_StreamSink), + .class_init =3D iopmp_transaction_info_sink_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_STREAM_SINK }, + { } + }, +}; + +static void +iopmp_register_types(void) +{ + type_register_static(&iopmp_info); + type_register_static(&iopmp_iommu_memory_region_info); + type_register_static(&transaction_info_sink); +} + +type_init(iopmp_register_types); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 85725506bf..4ae862ab80 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -330,3 +330,7 @@ djmemc_write(int reg, uint64_t value, unsigned int size= ) "reg=3D0x%x value=3D0x%"PRI # iosb.c iosb_read(int reg, uint64_t value, unsigned int size) "reg=3D0x%x value=3D= 0x%"PRIx64" size=3D%u" iosb_write(int reg, uint64_t value, unsigned int size) "reg=3D0x%x value= =3D0x%"PRIx64" size=3D%u" + +# riscv_iopmp.c +iopmp_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%x" +iopmp_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%x" diff --git a/include/hw/misc/riscv_iopmp.h b/include/hw/misc/riscv_iopmp.h new file mode 100644 index 0000000000..18a71e6f32 --- /dev/null +++ b/include/hw/misc/riscv_iopmp.h @@ -0,0 +1,187 @@ +/* + * QEMU RISC-V IOPMP (Input Output Physical Memory Protection) + * + * Copyright (c) 2023 Andes Tech. Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_IOPMP_H +#define RISCV_IOPMP_H + +#include "hw/sysbus.h" +#include "qemu/typedefs.h" +#include "memory.h" +#include "hw/stream.h" +#include "hw/misc/riscv_iopmp_transaction_info.h" +#include "hw/pci/pci_bus.h" + +#define TYPE_IOPMP "iopmp" +#define IOPMP(obj) OBJECT_CHECK(IopmpState, (obj), TYPE_IOPMP) + +#define IOPMP_MAX_MD_NUM 63 +#define IOPMP_MAX_SID_NUM 256 +#define IOPMP_MAX_ENTRY_NUM 512 + +#define VENDER_VIRT 0 +#define SPECVER_1_0_0_DRAFT4 4 + +#define IMPID_1_0_0_DRAFT4_0 10040 + +#define RRE_BUS_ERROR 0 +#define RRE_DECODE_ERROR 1 +#define RRE_SUCCESS_ZEROS 2 +#define RRE_SUCCESS_ONES 3 + +#define RWE_BUS_ERROR 0 +#define RWE_DECODE_ERROR 1 +#define RWE_SUCCESS 2 + +#define SIDSCP_OP_QUERY 0 +#define SIDSCP_OP_STALL 1 +#define SIDSCP_OP_NOTSTALL 2 + +#define ERR_REQINFO_TYPE_READ 0 +#define ERR_REQINFO_TYPE_WRITE 1 +#define ERR_REQINFO_TYPE_USER 3 + +#define IOPMP_MODEL_FULL 0 +#define IOPMP_MODEL_RAPIDK 0x1 +#define IOPMP_MODEL_DYNAMICK 0x2 +#define IOPMP_MODEL_ISOLATION 0x3 +#define IOPMP_MODEL_COMPACTK 0x4 +#define CFG_IOPMP_MODEL_K 8 + +#define CFG_TOR_EN 1 +#define CFG_SPS_EN 0 +#define CFG_USER_CFG_EN 0 +#define CFG_PROG_PRIENT 1 +#define CFG_PRIO_ENTRY IOPMP_MAX_ENTRY_NUM +#define CFG_SID_TRANSL_EN 0 +#define CFG_SID_TRANSL 0 + +#define ENTRY_NO_HIT 0 +#define ENTRY_PAR_HIT 1 +#define ENTRY_HIT 2 + +#define AXI_BURST_TYPE_FIX 0 +#define AXI_BURST_TYPE_INC 1 + +typedef enum { + IOPMP_AMATCH_OFF, /* Null (off) */ + IOPMP_AMATCH_TOR, /* Top of Range */ + IOPMP_AMATCH_NA4, /* Naturally aligned four-byte region */ + IOPMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ +} iopmp_am_t; + +typedef struct { + uint32_t addr_reg; + uint32_t addrh_reg; + uint32_t cfg_reg; +} iopmp_entry_t; + +typedef struct { + uint64_t sa; + uint64_t ea; +} iopmp_addr_t; + +typedef struct { + uint32_t srcmd_en[IOPMP_MAX_SID_NUM]; + uint32_t srcmd_enh[IOPMP_MAX_SID_NUM]; + uint32_t srcmd_r[IOPMP_MAX_SID_NUM]; + uint32_t srcmd_rh[IOPMP_MAX_SID_NUM]; + uint32_t srcmd_w[IOPMP_MAX_SID_NUM]; + uint32_t srcmd_wh[IOPMP_MAX_SID_NUM]; + uint32_t mdcfg[IOPMP_MAX_MD_NUM]; + iopmp_entry_t entry[IOPMP_MAX_ENTRY_NUM]; + uint32_t mdlck; + uint32_t mdlckh; + uint32_t entrylck; + uint32_t mdcfglck; + uint32_t arrlck; + uint32_t mdstall; + uint32_t mdstallh; + uint32_t sidscp; + uint32_t errreact; + uint64_t err_reqaddr; + uint32_t err_reqsid; + uint32_t err_reqinfo; +} iopmp_regs; + +/* To verfiy the same transcation */ +typedef struct iopmp_transaction_state { + bool supported; + bool running; + hwaddr start_addr; + hwaddr end_addr; +} iopmp_transaction_state; + +typedef struct iopmp_error_info { + uint32_t reqinfo; + hwaddr start_addr; + hwaddr end_addr; +} iopmp_error_info; + +typedef struct Iopmp_StreamSink { + Object parent; +} Iopmp_StreamSink; + +typedef struct iopmp_pci_as { + void *iopmp; + IOMMUMemoryRegion iommu; + AddressSpace as; +} iopmp_pci_addressspcace; + +typedef struct IopmpState { + SysBusDevice parent_obj; + iopmp_addr_t entry_addr[IOPMP_MAX_ENTRY_NUM]; + iopmp_transaction_state transaction_state[IOPMP_MAX_SID_NUM]; + QemuMutex iopmp_transaction_mutex; + iopmp_error_info prev_error_info[IOPMP_MAX_SID_NUM]; + MemoryRegion mmio; + IOMMUMemoryRegion iommu; + IOMMUMemoryRegion *next_iommu; + iopmp_regs regs; + MemoryRegion *downstream; + MemoryRegion blocked_io; + MemoryRegion stall_io; + char *model_str; + uint32_t model; + uint32_t k; + bool sps_en; + bool sid_transl_prog; + bool prient_prog; + bool sid_transl_en; + uint32_t sid_transl; + Iopmp_StreamSink transaction_info_sink; + + AddressSpace iopmp_sysbus_as; + iopmp_pci_addressspcace *iopmp_pci[IOPMP_MAX_SID_NUM]; + AddressSpace downstream_as; + AddressSpace blocked_io_as; + AddressSpace stall_io_as; + qemu_irq irq; + bool enable; + uint32_t sidscp_op[IOPMP_MAX_SID_NUM]; + uint64_t md_stall_stat; + uint32_t prio_entry; + + uint32_t sid_num; + uint32_t md_num; + uint32_t entry_num; +} IopmpState; + +void cascade_iopmp(DeviceState *cur_dev, DeviceState *next_dev); +void iopmp_setup_pci(DeviceState *iopmp_dev, PCIBus *bus); + +#endif diff --git a/include/hw/misc/riscv_iopmp_transaction_info.h b/include/hw/mi= sc/riscv_iopmp_transaction_info.h new file mode 100644 index 0000000000..fd12fd214c --- /dev/null +++ b/include/hw/misc/riscv_iopmp_transaction_info.h @@ -0,0 +1,28 @@ +/* + * QEMU RISC-V IOPMP (Input Output Physical Memory Protection) + * + * Copyright (c) 2023 Andes Tech. Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_IOPMP_TRANSACTION_INFO_H +#define RISCV_IOPMP_TRANSACTION_INFO_H + +typedef struct { + uint32_t sid:16; + uint64_t start_addr; + uint64_t end_addr; +} iopmp_transaction_info; + +#endif --=20 2.34.1 From nobody Sat Sep 21 05:26:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1705052726; cv=none; d=zohomail.com; s=zohoarc; b=RR70+L5QZrqDIHRgAhe8SSaM5/uAK3dnKQq+EOIeLGE/zDup9KevFOpZpTqGhiriEcdZXPg8OTdVfyra5QvpaMTGyuUGfhd52mxRdp+cpqEu2GMHVcr+6Ttunkxfd4RAAcJnUpxD5nWMVsL0RyVvlKNBHty6UrVsSd3W6oFf26U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1705052726; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=3ENj5NHPtwYVr/VvGba9TZnZ0GOrG8NX0M64cmQ/1zw=; b=b5E9g6BcYWlFETxbuT85V3T8HDDCwcSNH6F1/POooaLvINuQgfJqb+gVAEKDLh1hyNuUIvsee2icBh8LfxBcnEgemwLvOjmq2eR5/PGwoWvd5hs0xM0rS6WsOIBTuC+SuwU2BtjeEmvIOGXMwJNWsy2TQ6VAh5/w5ZpHzM3Zen8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17050527262190.8223349769530159; Fri, 12 Jan 2024 01:45:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rOE5T-0004eO-N8; Fri, 12 Jan 2024 04:44:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOE5N-0004ct-2p; Fri, 12 Jan 2024 04:44:22 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rOE5I-0005de-Vm; Fri, 12 Jan 2024 04:44:18 -0500 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 40C9hx8c060919; Fri, 12 Jan 2024 17:43:59 +0800 (+08) (envelope-from ethan84@andestech.com) Received: from ethan84-VirtualBox.andestech.com (10.0.12.51) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Fri, 12 Jan 2024 17:43:56 +0800 To: CC: , , , , , , , , Ethan Chen Subject: [PATCH v5 3/3] hw/riscv/virt: Add IOPMP support Date: Fri, 12 Jan 2024 17:43:35 +0800 Message-ID: <20240112094335.922010-4-ethan84@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240112094335.922010-1-ethan84@andestech.com> References: <20240112094335.922010-1-ethan84@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.12.51] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 40C9hx8c060919 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=ethan84@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Ethan Chen From: Ethan Chen via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1705052727278100001 Content-Type: text/plain; charset="utf-8" If a source device is connected to the IOPMP device, its memory transaction will be checked by the IOPMP rule. When using RISC-V virt machine option "iopmp=3Don", the generic PCIe host bridge connects to IOPMP. The PCI devices on the brigde will connets to IOPMP with default source id(SID) from PCI BDF. - Add 'iopmp=3Don' option to add an iopmp device. It checks dma operations from the generic PCIe host bridge. This option is assumed to be "off" - Add 'iopmp_cascade=3Don' option to add second iopmp device which is cascaded by first iopmp device to machine. When iopmp option is "off" , this option has no effect. Signed-off-by: Ethan Chen --- docs/system/riscv/virt.rst | 12 ++++ hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 110 ++++++++++++++++++++++++++++++++++++- include/hw/riscv/virt.h | 8 ++- 4 files changed, 129 insertions(+), 2 deletions(-) diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 9a06f95a34..e07ce2cd28 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -116,6 +116,18 @@ The following machine-specific options are supported: having AIA IMSIC (i.e. "aia=3Daplic-imsic" selected). When not specified, the default number of per-HART VS-level AIA IMSIC pages is 0. =20 +- iopmp=3D[on|off] + + When this option is "on". An IOPMP device is added to machine. It check= s dma + operations from the generic PCIe host bridge. This option is assumed to = be + "off". + +- iopmp_cascade=3D[on|off] + + When this option is "on". Second IOPMP device which is cascaded by first= IOPMP + device is added to machine. When IOPMP option is "off", this option has = no + effect. This option is assumed to be "off". + Running Linux kernel -------------------- =20 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a50717be87..c207b94747 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -46,6 +46,7 @@ config RISCV_VIRT select PLATFORM_BUS select ACPI select ACPI_PCI + select RISCV_IOPMP =20 config SHAKTI_C bool diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f9fd1341fc..c7a5035074 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -52,6 +52,7 @@ #include "hw/display/ramfb.h" #include "hw/acpi/aml-build.h" #include "qapi/qapi-visit-common.h" +#include "hw/misc/riscv_iopmp.h" =20 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU= . */ static bool virt_use_kvm_aia(RISCVVirtState *s) @@ -74,6 +75,8 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FW_CFG] =3D { 0x10100000, 0x18 }, + [VIRT_IOPMP] =3D { 0x10200000, 0x100000 }, + [VIRT_IOPMP2] =3D { 0x10300000, 0x100000 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, [VIRT_IMSIC_M] =3D { 0x24000000, VIRT_IMSIC_MAX_SIZE }, [VIRT_IMSIC_S] =3D { 0x28000000, VIRT_IMSIC_MAX_SIZE }, @@ -1011,6 +1014,44 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, con= st MemMapEntry *memmap) g_free(nodename); } =20 +static void create_fdt_iopmp(RISCVVirtState *s, const MemMapEntry *memmap, + uint32_t irq_mmio_phandle) { + char *name; + MachineState *ms =3D MACHINE(s); + + name =3D g_strdup_printf("/soc/iopmp@%lx", (long)memmap[VIRT_IOPMP].ba= se); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv_iopmp"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_IOPMP].b= ase, + 0x0, memmap[VIRT_IOPMP].size); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", IOPMP_IRQ); + } else { + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", IOPMP_IRQ, 0x4= ); + } + g_free(name); +} + +static void create_fdt_iopmp2(RISCVVirtState *s, const MemMapEntry *memmap, + uint32_t irq_mmio_phandle) { + char *name; + MachineState *ms =3D MACHINE(s); + + name =3D g_strdup_printf("/soc/iopmp2@%lx", (long)memmap[VIRT_IOPMP2].= base); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv_iopmp"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_IOPMP2].= base, + 0x0, memmap[VIRT_IOPMP2].size); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phan= dle); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", IOPMP2_IRQ); + } else { + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", IOPMP2_IRQ, 0x= 4); + } + g_free(name); +} + static void finalize_fdt(RISCVVirtState *s) { uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -1029,6 +1070,13 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_uart(s, virt_memmap, irq_mmio_phandle); =20 create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); + + if (s->have_iopmp) { + create_fdt_iopmp(s, virt_memmap, irq_mmio_phandle); + if (s->have_iopmp_cascade) { + create_fdt_iopmp2(s, virt_memmap, irq_mmio_phandle); + } + } } =20 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) @@ -1531,7 +1579,7 @@ static void virt_machine_init(MachineState *machine) qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); } =20 - gpex_pcie_init(system_memory, pcie_irqchip, s); + DeviceState *gpex_dev =3D gpex_pcie_init(system_memory, pcie_irqchip, = s); =20 create_platform_bus(s, mmio_irqchip); =20 @@ -1542,6 +1590,23 @@ static void virt_machine_init(MachineState *machine) sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, qdev_get_gpio_in(mmio_irqchip, RTC_IRQ)); =20 + if (s->have_iopmp) { + /* IOPMP */ + DeviceState *iopmp_dev =3D sysbus_create_simple(TYPE_IOPMP, + memmap[VIRT_IOPMP].base, + qdev_get_gpio_in(DEVICE(mmio_irqchip), IOPMP_IRQ)); + + /* PCI with IOPMP */ + iopmp_setup_pci(iopmp_dev, PCI_HOST_BRIDGE(gpex_dev)->bus); + + if (s->have_iopmp_cascade) { + DeviceState *iopmp_dev2 =3D sysbus_create_simple(TYPE_IOPMP, + memmap[VIRT_IOPMP2].base, + qdev_get_gpio_in(DEVICE(mmio_irqchip), IOPMP2_IRQ)); + cascade_iopmp(iopmp_dev, iopmp_dev2); + } + } + for (i =3D 0; i < ARRAY_SIZE(s->flash); i++) { /* Map legacy -drive if=3Dpflash to machine properties */ pflash_cfi01_legacy_drive(s->flash[i], @@ -1647,6 +1712,35 @@ static void virt_set_aclint(Object *obj, bool value,= Error **errp) s->have_aclint =3D value; } =20 +static bool virt_get_iopmp(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->have_iopmp; +} + +static void virt_set_iopmp(Object *obj, bool value, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->have_iopmp =3D value; +} + +static bool virt_get_iopmp_cascade(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + return s->have_iopmp_cascade; +} + +static void virt_set_iopmp_cascade(Object *obj, bool value, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->have_iopmp_cascade =3D value; +} + + bool virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi !=3D ON_OFF_AUTO_OFF; @@ -1749,6 +1843,20 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) NULL, NULL); object_class_property_set_description(oc, "acpi", "Enable ACPI"); + + object_class_property_add_bool(oc, "iopmp", virt_get_iopmp, + virt_set_iopmp); + object_class_property_set_description(oc, "iopmp", + "Set on/off to enable/disable " + "iopmp device"); + + object_class_property_add_bool(oc, "iopmp-cascade", + virt_get_iopmp_cascade, + virt_set_iopmp_cascade); + object_class_property_set_description(oc, "iopmp-cascade", + "Set on/off to enable/disable " + "iopmp2 device which is cascaded= by " + "iopmp1 device"); } =20 static const TypeInfo virt_machine_typeinfo =3D { diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index f89790fd58..07d95fde61 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,6 +55,8 @@ struct RISCVVirtState { =20 int fdt_size; bool have_aclint; + bool have_iopmp; + bool have_iopmp_cascade; RISCVVirtAIAType aia_type; int aia_guests; char *oem_id; @@ -84,12 +86,16 @@ enum { VIRT_PCIE_MMIO, VIRT_PCIE_PIO, VIRT_PLATFORM_BUS, - VIRT_PCIE_ECAM + VIRT_PCIE_ECAM, + VIRT_IOPMP, + VIRT_IOPMP2, }; =20 enum { UART0_IRQ =3D 10, RTC_IRQ =3D 11, + IOPMP_IRQ =3D 12, + IOPMP2_IRQ =3D 13, VIRTIO_IRQ =3D 1, /* 1 to 8 */ VIRTIO_COUNT =3D 8, PCIE_IRQ =3D 0x20, /* 32 to 35 */ --=20 2.34.1