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([102.35.208.160]) by smtp.gmail.com with ESMTPSA id h7-20020adff4c7000000b0033677aae2e2sm1349000wrp.107.2024.01.11.06.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 06:24:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704983053; x=1705587853; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zp8qrWUcSTBg18ScDzokCUU9rq/1sFICSbhnSWqMC94=; b=jOBzJuTAYdM4hrQg3vHJbgL0SBKDfNmaFiyqQ1indKmHghHifplZ/IK1WIq4N/Yj5P 3j9x5FUbKaREicdC59mZ16Tx3H+B1u8+c9jmWRiaGVmLghHTW0DX/4nrMulF7mJbbrnX taFa5q3hN2/6lB3iNi4XoaIqaojRpRYCI8MPqaIlDcPNA3Q3+w47BHfovuZx7dHn4Hfl 8sE/n086eGaSlJFJvLaovrDgGJBCreZ4TtWwWRPeHqxEeef6LGW42vao9UFu8ryw0SSB vWa/z86wshucagdHhNrCUXqp24Uc4fQJI06BtMzhQnP+grUHH436Qh6xML9B3FHYUdyl xKrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704983053; x=1705587853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zp8qrWUcSTBg18ScDzokCUU9rq/1sFICSbhnSWqMC94=; b=Y94/+/Ed4YNEHsmemVNiL2TBSPU+RkWLr5lk5hsH4Lyve5Izd/9xuGHc3U6xrRxBGJ 0/N0HuxtoKe0RYYYRJu61SAKoy10ucVzq4PGGbsC3u9t5oqIo821IVD82GfvD6aigY/J A3m0jTA5uowovMRJmWXnFK9t7rMxFugvKZYUO96vhCFMolugSTEdbxArJYD+KpikK+wu YAoan/YxzFBjDa1mUMFYDReI2PWYsxFNXvExEUJx/AhnEDBan3LZg5skaxDvhjLSbuER fFoVQKrzYcmNju8C5DjCuoZ/FYdG00dl4sJM/Dy2pVs4SaMat+3gXvRKW2QZySmLZswW l+gA== X-Gm-Message-State: AOJu0YxPMgU5Jqs6m6Eg4E0Ddh7ZnQxGJv48FvMWmBPFat/h7dOXDgrD AdjB6+3MRyvoaQatXuYlGoOrjSHvUK+yYlcFla5oJey3bYvdeQ== X-Google-Smtp-Source: AGHT+IEp8rBMaXKYeM9XjQ1ZNn2LNh9Pau6jIAhZdW5iD7ovwjWAMoO3m3b4Aa1oZ+Cq8ZAtcSzdcA== X-Received: by 2002:adf:ed0a:0:b0:337:3e7d:11bc with SMTP id a10-20020adfed0a000000b003373e7d11bcmr589416wro.107.1704983053331; Thu, 11 Jan 2024 06:24:13 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: Pierrick Bouvier , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Mahmoud Mandour , Richard Henderson , Paolo Bonzini , Alexandre Iooss Subject: [PATCH 11/12] plugins: remove non per_vcpu inline operation from API Date: Thu, 11 Jan 2024 18:23:24 +0400 Message-ID: <20240111142326.1743444-12-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240111142326.1743444-1-pierrick.bouvier@linaro.org> References: <20240111142326.1743444-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=pierrick.bouvier@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704983160158100001 Content-Type: text/plain; charset="utf-8" Now we have a thread-safe equivalent of inline operation, and that all plugins were changed to use it, there is no point to keep the old API. In more, it will help when we implement more functionality (conditional callbacks), as we know can assume that all inline operation have an offset associated. In case a user still want the old behaviour (target a single memory location), it's still possible to define an inline operation with a 0 offset. Bump API version as it's a breaking change for existing plugins. Signed-off-by: Pierrick Bouvier --- include/qemu/qemu-plugin.h | 59 ++++---------------------------------- plugins/api.c | 22 -------------- 2 files changed, 6 insertions(+), 75 deletions(-) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 8a0691a760e..65e770f5c56 100644 --- a/include/qemu/qemu-plugin.h +++ b/include/qemu/qemu-plugin.h @@ -50,11 +50,16 @@ typedef uint64_t qemu_plugin_id_t; * * The plugins export the API they were built against by exposing the * symbol qemu_plugin_version which can be checked. + * + * Version 2: + * Remove qemu_plugin_register_vcpu_{tb, insn, mem}_exec_inline. + * Those functions are replaced by *_per_vcpu variants, which guarantees + * thread-safety for operations. */ =20 extern QEMU_PLUGIN_EXPORT int qemu_plugin_version; =20 -#define QEMU_PLUGIN_VERSION 1 +#define QEMU_PLUGIN_VERSION 2 =20 /** * struct qemu_info_t - system information for plugins @@ -293,25 +298,6 @@ enum qemu_plugin_op { QEMU_PLUGIN_INLINE_ADD_U64, }; =20 -/** - * qemu_plugin_register_vcpu_tb_exec_inline() - execution inline op - * @tb: the opaque qemu_plugin_tb handle for the translation - * @op: the type of qemu_plugin_op (e.g. ADD_U64) - * @ptr: the target memory location for the op - * @imm: the op data (e.g. 1) - * - * Insert an inline op to every time a translated unit executes. - * Useful if you just want to increment a single counter somewhere in - * memory. - * - * Note: ops are not atomic so in multi-threaded/multi-smp situations - * you will get inexact results. - */ -QEMU_PLUGIN_API -void qemu_plugin_register_vcpu_tb_exec_inline(struct qemu_plugin_tb *tb, - enum qemu_plugin_op op, - void *ptr, uint64_t imm); - /** * qemu_plugin_register_vcpu_tb_exec_inline_per_vcpu() - execution inline = op * @tb: the opaque qemu_plugin_tb handle for the translation @@ -346,21 +332,6 @@ void qemu_plugin_register_vcpu_insn_exec_cb(struct qem= u_plugin_insn *insn, enum qemu_plugin_cb_flags flag= s, void *userdata); =20 -/** - * qemu_plugin_register_vcpu_insn_exec_inline() - insn execution inline op - * @insn: the opaque qemu_plugin_insn handle for an instruction - * @op: the type of qemu_plugin_op (e.g. ADD_U64) - * @ptr: the target memory location for the op - * @imm: the op data (e.g. 1) - * - * Insert an inline op to every time an instruction executes. Useful - * if you just want to increment a single counter somewhere in memory. - */ -QEMU_PLUGIN_API -void qemu_plugin_register_vcpu_insn_exec_inline(struct qemu_plugin_insn *i= nsn, - enum qemu_plugin_op op, - void *ptr, uint64_t imm); - /** * qemu_plugin_register_vcpu_insn_exec_inline_per_vcpu() - insn exec inlin= e op * @insn: the opaque qemu_plugin_insn handle for an instruction @@ -585,24 +556,6 @@ void qemu_plugin_register_vcpu_mem_cb(struct qemu_plug= in_insn *insn, enum qemu_plugin_mem_rw rw, void *userdata); =20 -/** - * qemu_plugin_register_vcpu_mem_inline() - register an inline op to any m= emory access - * @insn: handle for instruction to instrument - * @rw: apply to reads, writes or both - * @op: the op, of type qemu_plugin_op - * @ptr: pointer memory for the op - * @imm: immediate data for @op - * - * This registers a inline op every memory access generated by the - * instruction. This provides for a lightweight but not thread-safe - * way of counting the number of operations done. - */ -QEMU_PLUGIN_API -void qemu_plugin_register_vcpu_mem_inline(struct qemu_plugin_insn *insn, - enum qemu_plugin_mem_rw rw, - enum qemu_plugin_op op, void *pt= r, - uint64_t imm); - /** * qemu_plugin_register_vcpu_mem_inline_per_vcpu() - inline op for mem acc= ess * @insn: handle for instruction to instrument diff --git a/plugins/api.c b/plugins/api.c index fd6ce678501..a51585b3e53 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -94,13 +94,6 @@ void qemu_plugin_register_vcpu_tb_exec_cb(struct qemu_pl= ugin_tb *tb, } } =20 -void qemu_plugin_register_vcpu_tb_exec_inline(struct qemu_plugin_tb *tb, - enum qemu_plugin_op op, - void *ptr, uint64_t imm) -{ - qemu_plugin_register_vcpu_tb_exec_inline_per_vcpu(tb, op, ptr, 0, imm); -} - void qemu_plugin_register_vcpu_tb_exec_inline_per_vcpu( struct qemu_plugin_tb *tb, enum qemu_plugin_op op, @@ -124,13 +117,6 @@ void qemu_plugin_register_vcpu_insn_exec_cb(struct qem= u_plugin_insn *insn, } } =20 -void qemu_plugin_register_vcpu_insn_exec_inline(struct qemu_plugin_insn *i= nsn, - enum qemu_plugin_op op, - void *ptr, uint64_t imm) -{ - qemu_plugin_register_vcpu_insn_exec_inline_per_vcpu(insn, op, ptr, 0, = imm); -} - void qemu_plugin_register_vcpu_insn_exec_inline_per_vcpu( struct qemu_plugin_insn *insn, enum qemu_plugin_op op, @@ -158,14 +144,6 @@ void qemu_plugin_register_vcpu_mem_cb(struct qemu_plug= in_insn *insn, cb, flags, rw, udata); } =20 -void qemu_plugin_register_vcpu_mem_inline(struct qemu_plugin_insn *insn, - enum qemu_plugin_mem_rw rw, - enum qemu_plugin_op op, void *pt= r, - uint64_t imm) -{ - qemu_plugin_register_vcpu_mem_inline_per_vcpu(insn, rw, op, ptr, 0, im= m); -} - void qemu_plugin_register_vcpu_mem_inline_per_vcpu( struct qemu_plugin_insn *insn, enum qemu_plugin_mem_rw rw, --=20 2.43.0