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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971110; x=1705575910; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yscuAN2+W6F+E5GdpmQyLDg77dRJm7PXwcNzo7tUEdc=; b=PGa+d2ENAu+hfpA/yLS4+K6lpMvx491mlQ0r22T64WeQdY8apOzbrGKDg3nImZpWru h24mbNXspVkRflkTLRala0NUGV0N49CDhT/KBUw67tbxolu2iQVRjwU2IHkhOgfawUgy iFDH0CPAqY732B5Azvom9/0+DECcvHBI82aSZYbpx8IUkc8Xv2y6HlAg4ysO8Mz24+M2 wnERQAZVo3nf5qNKKfY2tpa0j9oMNmBSqBwzapjou/G0Ik2xv44XmfW/Xbdm3aCcLlBz BbglE7/Qmln5KnnHkbs3jn4E5V171R9AVYvZCIWXpNdzgLl3bXT4M4PRNlBR9JAr3iXb ruRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971110; x=1705575910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yscuAN2+W6F+E5GdpmQyLDg77dRJm7PXwcNzo7tUEdc=; b=JSm7lbed8mnwABULrgcbLI2VsEwonrnQqhTi8gLzgQhzqfEjcI31iYYuP03PzYOQqj dDq15UP0KCQhKbHtwBvMiDUUixXI4kN4PkZ705Uvjic4Uk1MPgV+RKzwhXpxDAjXOjIO Dz2Fl8GiSFB4uqd+3U3hCiDjfoT/+sI5VO2KK93D2bGK/gZ8UgcjkwP+vfnMMvQvoWwb EDWX4Rr+nmHSN6tE5ibApMfYjbA9peuUOSGf1XZXr3MAoNtW9LTmu/jEZ1Rsdrz7E2bH LNvxKCRoKpIYGOMynqP6tQNl3N7qpnBjk4u1p+hgVXnyjSsILiV5LEJCxveItnAKWPUy dKhg== X-Gm-Message-State: AOJu0YwMGigxt94wHBPkCXLVz26yT5fqmnDWcixl1ew6kJfrMb76atDU ThXzntlsTIhB2acba1W4TB/z9cBVstAb8pF97ccLKvxF5mU= X-Google-Smtp-Source: AGHT+IEzeVr7AsJQFCTYxbAjWqPQybHomtJI7ETWz/juZox6lFz3CGmo3jIptZo/x+RG7X2DJoVqpQ== X-Received: by 2002:adf:a183:0:b0:336:7608:d0f4 with SMTP id u3-20020adfa183000000b003367608d0f4mr421626wru.17.1704971110593; Thu, 11 Jan 2024 03:05:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU Date: Thu, 11 Jan 2024 11:04:32 +0000 Message-Id: <20240111110505.1563291-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704971531884100001 Content-Type: text/plain; charset="utf-8" The CTR_EL0 register has some bits which allow the implementation to tell the guest that it does not need to do cache maintenance for data-to-instruction coherence and instruction-to-data coherence. QEMU doesn't emulate caches and so our cache maintenance insns are all NOPs. We already have some models of specific CPUs where we set these bits (e.g. the Neoverse V1), but the 'max' CPU still uses the settings it inherits from Cortex-A57. Set the bits for 'max' as well, so the guest doesn't need to do unnecessary work. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/tcg/cpu64.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fcda99e1583..40e7a45166f 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1105,6 +1105,16 @@ void aarch64_max_tcg_initfn(Object *obj) u =3D FIELD_DP32(u, CLIDR_EL1, LOUU, 0); cpu->clidr =3D u; =20 + /* + * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to + * do any cache maintenance for data-to-instruction or + * instruction-to-guest coherence. (Our cache ops are nops.) + */ + t =3D cpu->ctr; + t =3D FIELD_DP64(t, CTR_EL0, IDC, 1); + t =3D FIELD_DP64(t, CTR_EL0, DIC, 1); + cpu->ctr =3D t; + t =3D cpu->isar.id_aa64isar0; t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ --=20 2.34.1