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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971123; x=1705575923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WQZ9joUzytLik4j8W+c4JeBQFuz0jyAB3AYXVmNfQ3M=; b=yIFQmENbNTkWx9E2R+KHebFYaEm+GKWSKrT6/F8Pk6QqtGh/g+Ky1Edk2yw8s778Li I5KT9Xaft6O3AeuWzVM+Rcik4k1RYAlniiGpCUZBBFqv6dNweclKb6U/43tq5tOMJvbu aR2bnjUtxPUEqSDStwGZ7N/FGqlfLBPl783GAYydf2z0N9FwlWUQwk1DUSr6o88d9Ep2 p6BH/kWmqLVFkn6i9jbSHoCbrATdV0xYNtS42Rv4UADckzCTPPOsovcjKLMFuDFT1+xU yw5dLN5oyPSKbj4qjz5TjPJQi4IwVrmwwXuojzwUVoINYysch2VNelbh79uNxqn7RqZO ZLDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971123; x=1705575923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WQZ9joUzytLik4j8W+c4JeBQFuz0jyAB3AYXVmNfQ3M=; b=RknYjNfVR/3nPoyFnEezSkb7LMsEUANfsVWLjdezdTqFPOkzDuekP97K1vstPwxGN+ 8g+uvPBoOkROxdT2HFiER0/ZgJg86XYz9GmcgxJTnG8oRS2KBgmgVarBIoZy+4J0eddq IaG5mGbvKGj3/KwaCW+7qe3fwImPQ6HrQqXzoUdoHg/1MjxrQn62KlroHgeSbZbPbshO sb66XPRp12q3Yt5vWk1LuIMw/fA+fei3nxyvxZLV5YxT2h82AIBW1MVbxDVZBc5TI2Fj p0rizatqSr005CM/zydI9EiFBJrFOhM2H/NHCIpFs2AEhW5NPjs5Kkn9Axa6Eviy8F8b mdPg== X-Gm-Message-State: AOJu0YwXgay7WywqPWUkkjzON2J7nvn1EVoxKlKsJogYDKlYDrgvNonO SvRri8J//7pfHLfFWXYmfxgc4fNkrZWykZKHAMFDs8vbbi0= X-Google-Smtp-Source: AGHT+IFUI6h5Hgo4RLVvwOug8Mr6DG68K3Z2IiQH7X28Yr3RZZxpKznqaBgX4JQSZHb28NilUFYm/g== X-Received: by 2002:adf:ec48:0:b0:337:61e3:7421 with SMTP id w8-20020adfec48000000b0033761e37421mr546032wrn.44.1704971123589; Thu, 11 Jan 2024 03:05:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/41] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers Date: Thu, 11 Jan 2024 11:05:02 +0000 Message-Id: <20240111110505.1563291-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704971435480100007 Content-Type: text/plain; charset="utf-8" Mark up the cpreginfo structs for the GIC CPU registers to indicate the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- hw/intc/arm_gicv3_cpuif.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 6ac90536402..e1a60d8c15b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2684,6 +2684,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { { .name =3D "ICH_AP0R0_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 8, .opc2 =3D 0, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x480, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2691,6 +2692,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { { .name =3D "ICH_AP1R0_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 9, .opc2 =3D 0, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x4a0, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2698,6 +2700,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { { .name =3D "ICH_HCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 11, .opc2 =3D 0, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x4c0, .access =3D PL2_RW, .readfn =3D ich_hcr_read, .writefn =3D ich_hcr_write, @@ -2729,6 +2732,7 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { { .name =3D "ICH_VMCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 11, .opc2 =3D 7, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x4c8, .access =3D PL2_RW, .readfn =3D ich_vmcr_read, .writefn =3D ich_vmcr_write, @@ -2739,6 +2743,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_regin= fo[] =3D { { .name =3D "ICH_AP0R1_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 8, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x488, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2746,6 +2751,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_regin= fo[] =3D { { .name =3D "ICH_AP1R1_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 9, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x4a8, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2756,6 +2762,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { { .name =3D "ICH_AP0R2_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 8, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x490, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2763,6 +2770,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { { .name =3D "ICH_AP0R3_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 8, .opc2 =3D 3, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x498, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2770,6 +2778,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { { .name =3D "ICH_AP1R2_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 9, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x4b0, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2777,6 +2786,7 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { { .name =3D "ICH_AP1R3_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 9, .opc2 =3D 3, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x4b8, .access =3D PL2_RW, .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, @@ -2898,6 +2908,7 @@ void gicv3_init_cpuif(GICv3State *s) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 12 + (j >> 3), .opc2 =3D j & 7, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .nv2_redirect_offset =3D 0x400 + 8 * j, .access =3D PL2_RW, .readfn =3D ich_lr_read, .writefn =3D ich_lr_write, --=20 2.34.1