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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971123; x=1705575923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HjbFqOWn/TNSc9et6xxdifrEZI+6S3bwTcQGRjFtcY4=; b=TkmOJpH3XsOxFLEDJc+vidQcHmFsJm4AcE4ih+O4ivlt9UWQwBGdqJuzcZy4BVqbwL VgFkCIIv1vzlVcl/BMfwkPkX+yuAwyvLW6pPr0tnLFHOfpMXvC77dPl55E7d86eFN5ws 0JQa3yKbZoJAtRsXZ5gIWyorISN6gmr40rfnmBZSLsGxzndqkuqPXRU/ck2il/VE9WgU Ka/qWB7tD3N0LnJNdJkYhIkZdL0veB6oGj3CdREaS84LqZM8Zdwn7vje4UxqVqGmYpaU 4l1CtjwKXKtnR2YO4hGaqkyCp/wdaoOMyPgIc7QAS50jAzCDX7O22LBoHd8uvthieQtI h4oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971123; x=1705575923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HjbFqOWn/TNSc9et6xxdifrEZI+6S3bwTcQGRjFtcY4=; b=r3NIXjhw+U8LKOhHJKJwD7WO0FA5LFnwFH92qkCrqNSeE03uiXo4yWJzXlhh0HcZOi 8lC8AEi0eliSr33pOdwFcZD18GF+wOET8P2jjI4MmOrYRQ2dZR2CNAyzmZTaWANGmk7i LgjKZZPG7lPHDSL5+R2CYhFEXZSnEi2puE1LUbYtr3i24jGNOaRPUEqFCO/oNfLO/WEz 0Jf9Qt1jT3jBSuFCXsujTV5Oa5zD5Be6KF59ypVj3slug/aTgBcoUmOqub2SDSGxflYp RPNNsCvMYdTem2QzfNpnOTanw+WFbQxVExkaxQKBAgodn1mRG39BrUOf6pvk/2gizhqG e6VQ== X-Gm-Message-State: AOJu0YzbXPuZa5OvRPmN5wA4SfjTRqr45bUEBicstnlyqvKuEeNgF1Cj XRDzBoExVh1HvIf9rBEEH7XwlTtScgRpx/M0iEaZFRsz33c= X-Google-Smtp-Source: AGHT+IE/sPSZZPsCY5jZsS0z5tILk+1K0PeTw31TDh9i5+dOdfwQwcpzC0osduDYVNg79evRsmycvQ== X-Received: by 2002:a05:600c:3491:b0:40e:5d36:8bb0 with SMTP id a17-20020a05600c349100b0040e5d368bb0mr271602wmq.44.1704971123180; Thu, 11 Jan 2024 03:05:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/41] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) Date: Thu, 11 Jan 2024 11:05:01 +0000 Message-Id: <20240111110505.1563291-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704971316823100001 Content-Type: text/plain; charset="utf-8" Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This covers all the remaining offsets at 0x200 and above, except for the GIC ICH_* registers. (Note that because we don't implement FEAT_SPE, FEAT_TRF, FEAT_MPAM, FEAT_BRBE or FEAT_AMUv1p1 we don't implement any of the registers that use offsets at 0x800 and above.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index aa66f5169ab..4550ff7ffde 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4287,6 +4287,7 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_FAR_EL1, + .nv2_redirect_offset =3D 0x220 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -4302,6 +4303,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, + .nv2_redirect_offset =3D 0x200 | NV2_REDIR_NV1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, @@ -4309,6 +4311,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, + .nv2_redirect_offset =3D 0x210 | NV2_REDIR_NV1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -5741,6 +5744,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_nv1, + .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, @@ -5760,6 +5764,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .nv2_redirect_offset =3D 0x240, .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, @@ -6882,9 +6887,11 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .nv2_redirect_offset =3D 0x500, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .nv2_redirect_offset =3D 0x508, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, }; =20 @@ -9548,6 +9555,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_RW, .writefn =3D vbar_write, .accessfn =3D access_nv1, .fgt =3D FGT_VBAR_EL1, + .nv2_redirect_offset =3D 0x250 | NV2_REDIR_NV1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, --=20 2.34.1