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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971123; x=1705575923; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WIRlikOf+Qay01mq3PzxaBC1vuA3jtjYGSPSXLeA82A=; b=XCnQAlISTS3twzGAPwmcQJ/yD02xa19Z8AB7XEJNc9/ykP9HVPRB6Oh7gyeYL3wiFq KwjnvyYVqZSaCbp1PsSD5fCH1qMcXUwtXSszcdxCMuhZqy0+AgKy2TNOeWODu0rWuGXl WP9X4Ve4peZqEyCU/CQV3kKcAQlc53PluGASfIviCh3tmg28WrF6OOFkCWXJYXHBvxlA FYvfAL8HdkmXVKbC+BQ+dTwjWSZBZmb+NYEJHp0SWRKoOBsVXK0DoDzheRK6x6PogYKg Zzxo2Q3B+xy8qUxjVL7YVI0QQep4p3XA2terscCF/+9heaj20KTy2Z9dgf3IwAwZztgn Cutw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971123; x=1705575923; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WIRlikOf+Qay01mq3PzxaBC1vuA3jtjYGSPSXLeA82A=; b=IeYgcIDeVz0fEXqzdYRe9qXIRr/mBr6EqIjYoQei6NbMVKUOwXU1qGAG1GmuTPUKFF P3Anu3oulbQGAHoEaR29rLSiAu4gon19NPTmInVYYjtDuiwY242Uhsb/MYxVuRnxSCz3 ERFUsr/giCJg7n19zNq+KD+PV+IwTNRBSnPD/kqHBBslaqk1/+c2zncRn8H+7EWi5eUl YWa2ABSypCnLlPE/vXgL7xysZajMB9Kv2BdPnfJxxsjTYSsV3I2WqbqTRw7LO7iWdPJh 5p+cVZQ5lOqHn+AujViNd2RNtqZRg0XW2c85dFTgln7hnRYM2z4hOymeb8ChopF+SBuE MRCA== X-Gm-Message-State: AOJu0Yz0ic88AyKI+u1KWdintkPM9Qo8KqB17y+ft1gmXJ7f4ixvzH1w 68CD75ee8+kl40zObfxa4+RsCPl6NCufrD5wpAeAS2kNu6Y= X-Google-Smtp-Source: AGHT+IGa6cxL7DAc35zfJHDD2MZ26BuL8DJWF3oGMjwRMvr04wWxcos8ivs8a0rtGvB5UIZA55sVOA== X-Received: by 2002:adf:cc8b:0:b0:337:3a52:9aa6 with SMTP id p11-20020adfcc8b000000b003373a529aa6mr587453wrj.39.1704971122771; Thu, 11 Jan 2024 03:05:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/41] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) Date: Thu, 11 Jan 2024 11:05:00 +0000 Message-Id: <20240111110505.1563291-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704971465652100007 Content-Type: text/plain; charset="utf-8" Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets 0x168 to 0x1f8. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1d62d243cdc..aa66f5169ab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3191,6 +3191,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, + .nv2_redirect_offset =3D 0x180 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .resetvalue =3D 0, .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, @@ -3208,6 +3209,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, + .nv2_redirect_offset =3D 0x170 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .resetvalue =3D 0, .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, @@ -3287,6 +3289,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_IO, + .nv2_redirect_offset =3D 0x178 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, @@ -3304,6 +3307,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_IO, + .nv2_redirect_offset =3D 0x168 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, @@ -7052,6 +7056,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_reginfo[] =3D { { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .nv2_redirect_offset =3D 0x1e0 | NV2_REDIR_NV1, .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }, @@ -7193,6 +7198,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .writefn =3D svcr_write, .raw_writefn =3D raw_write }, { .name =3D "SMCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, + .nv2_redirect_offset =3D 0x1f0 | NV2_REDIR_NV1, .access =3D PL1_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[1]), .writefn =3D smcr_write, .raw_writefn =3D raw_write }, @@ -7226,6 +7232,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "SMPRIMAP_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 5, + .nv2_redirect_offset =3D 0x1f8, .access =3D PL2_RW, .accessfn =3D access_smprimap, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; @@ -7948,6 +7955,7 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tfsr_el1, + .nv2_redirect_offset =3D 0x190 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_NV2_REDIRECT, @@ -8122,6 +8130,7 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_scxtnum_el1, .fgt =3D FGT_SCXTNUM_EL1, + .nv2_redirect_offset =3D 0x188 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -8146,22 +8155,27 @@ static CPAccessResult access_fgt(CPUARMState *env, = const ARMCPRegInfo *ri, static const ARMCPRegInfo fgt_reginfo[] =3D { { .name =3D "HFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .nv2_redirect_offset =3D 0x1b8, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR])= }, { .name =3D "HFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 5, + .nv2_redirect_offset =3D 0x1c0, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]= ) }, { .name =3D "HDFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 4, + .nv2_redirect_offset =3D 0x1d0, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]= ) }, { .name =3D "HDFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 5, + .nv2_redirect_offset =3D 0x1d8, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR= ]) }, { .name =3D "HFGITR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 6, + .nv2_redirect_offset =3D 0x1c8, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR])= }, }; @@ -8348,12 +8362,14 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D e2h_access, + .nv2_redirect_offset =3D 0x180 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D e2h_access, + .nv2_redirect_offset =3D 0x170 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, @@ -8370,11 +8386,13 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .nv2_redirect_offset =3D 0x178 | NV2_REDIR_NO_NV1, .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .nv2_redirect_offset =3D 0x168 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, --=20 2.34.1