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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971118; x=1705575918; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eJ2Bh2KqWHFGhwYEJgAtL+OLtHKA2aP7b6zI0XswIFc=; b=DsriuO8dhxbadttNkhkihV2kjaBlI3gnEnhwUomciI134r7uChbnBLUNNc68RLOS+3 zneqOPRRXVcq3TdLNU909eer9zZGsDKIRdJPtG9cEUsKuhcfVV05z3z4CErJWWMXyCxR 5+st7BqwluPO48wyyei9RoA2VGqfAGMwoUs03H9b2BCkjQ0fa9UYZ79TTQDWpQLSIjcp iDJ1AmU9c8wlMmCFM46vyUQc/p3b3RsKbeeyCAZImdpuO3kpGJcJe1hmNN6HCr8IV/uI t0L0klLWk/PjYSrEV16bQUpOj4opeH1Uz4e/uhoV77mQDa20xuMyjVHb+ks75w1l9B/I gbzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971118; x=1705575918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eJ2Bh2KqWHFGhwYEJgAtL+OLtHKA2aP7b6zI0XswIFc=; b=KkB3ZdZ6gVEOoXw2lRIDRvlOOpA7GnsXpEPglpmEWF4in9RcYfJ96XMhg7//No+rk+ TkB3OlOKFqwy566Qiguu2v/0L8FEGB3kKDZKW7fkWWjUWuS8cxBbmVOVyll50/NHxuFI QZ2ClwkGpF94FtxSdKaJ1EfFkQkXnsOGj+daqxd8A0n5/kI98fMVrh7cq/kCIlnHJZqS GRgfTmcJpXHre6R/hI0UPc3DVqzLYxvzFk6BbOPk5fBXlElpCAv/XfLREwIF85tr2F0r eHGaCTyD/QeUwr/0YJ9fbsqRiYktYvFIOvSrnv4YZ9OEWABbVKrRezxCP8zX5x1nb7o/ 7oRw== X-Gm-Message-State: AOJu0Yxe/7/jBPPmg14+e2CYFjknQPEoy7F1svfAsL2tqFFptaGFVdWD zq7sNtD3YpL8maRq/32qdT1Vf4SJ0KbYr4eupLVc4LuEYpQ= X-Google-Smtp-Source: AGHT+IGxFtRsWhV4yNdjp6bYNE+WmJYPJReM9C8o5SvFBJtCtY8oI+fxc92AAwPjDcyIRR8DOcGRIg== X-Received: by 2002:a05:600c:520d:b0:40e:622f:ebf with SMTP id fb13-20020a05600c520d00b0040e622f0ebfmr128544wmb.178.1704971118097; Thu, 11 Jan 2024 03:05:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/41] target/arm: Handle FEAT_NV page table attribute changes Date: Thu, 11 Jan 2024 11:04:50 +0000 Message-Id: <20240111110505.1563291-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704971198259100002 Content-Type: text/plain; charset="utf-8" FEAT_NV requires that when HCR_EL2.{NV,NV1} =3D=3D {1,1} the handling of some of the page table attribute bits changes for the EL1&0 translation regime: * for block and page descriptors: - bit [54] holds PXN, not UXN - bit [53] is RES0, and the effective value of UXN is 0 - bit [6], AP[1], is treated as 0 * for table descriptors, when hierarchical permissions are enabled: - bit [60] holds PXNTable, not UXNTable - bit [59] is RES0 - bit [61], APTable[0] is treated as 0 Implement these changes to the page table attribute handling. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/ptw.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0ecd3a36dad..2d4fa8dbcaf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1581,6 +1581,12 @@ static bool lpae_block_desc_valid(ARMCPU *cpu, bool = ds, } } =20 +static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw) +{ + uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, ptw->in_space); + return (hcr & (HCR_NV | HCR_NV1)) =3D=3D (HCR_NV | HCR_NV1); +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * @@ -1989,6 +1995,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, xn =3D extract64(attrs, 54, 1); pxn =3D extract64(attrs, 53, 1); =20 + if (el =3D=3D 1 && nv_nv1_enabled(env, ptw)) { + /* + * With FEAT_NV, when HCR_EL2.{NV,NV1} =3D=3D {1,1}, the block= /page + * descriptor bit 54 holds PXN, 53 is RES0, and the effective = value + * of UXN is 0. Similarly for bits 59 and 60 in table descript= ors + * (which we have already folded into bits 53 and 54 of attrs). + * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. + * Similarly, APTable[0] from the table descriptor is treated = as 0; + * we already folded this into AP[1] and squashing that to 0 d= oes + * the right thing. + */ + pxn =3D xn; + xn =3D 0; + ap &=3D ~1; + } /* * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security space. --=20 2.34.1