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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v30-20020adf8b5e000000b0033690139ea5sm951323wra.44.2024.01.11.03.05.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 03:05:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704971111; x=1705575911; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MggGO+NPAbBJmsyAFGskbOZEUDcciWvWwdLwaUXekp4=; b=k0fUZ55OnwPMRbZdtr9VeijGOF4Ni+eQP/QtBskG2QKY50YQ7IXU3Woa23gaW+IV4A cebyHUGIl8oVbgfkoYh0v/9/G8B4q0J/58nfAiOF3Mxv/Teb+f5ojOs3cscoCszJ9pmn KmPp4WD48+ar3Ae/xkKCyxJnlqSksFuU/UW5h8ciW1AyAkBxqSlIDDBrRGGlRFDNFsQc rjx5PBjq5H41kVZxjWlzaorqP/nABci2n0xaIBR9XhrcQUCGxm9WWINYondTWu+oJSK5 p6lCLDFCUl4zPWcC5VMYpb1BiAyy2BWsrnetOPrACqzWRFbs6h3S0RvQwyaOsgpp02Qa IEkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704971111; x=1705575911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MggGO+NPAbBJmsyAFGskbOZEUDcciWvWwdLwaUXekp4=; b=HG3eRKn3uU+PKAdBNqjTAMZg8HUQKaJo0cK6rKfDFl+s8jv9v+a8K7Ufsa/zCF0xO4 BPEhlHx6/Zje0NSkWBORTFhJyOxsDjCB4whFHLYAjFv5tGshkLS4YdtoqGRZP8E6mDd0 Ask2JF9lIbiySv2wyjmK/bj1ksRSWuya+64ziYbXSTyOnRsnICQZNx+Qf/iS2/i6UP2v 1C30UCH8ONkenyRuOKjF5kjFErICEPjXgFlFHNZM4STNfraftvdm6+bCXsT8QIoi3roB 5WSlxZhTQObg+s8m7EUJl1dpOcgXko2V8kcte+T4iNgsBfeZb9jAxhmwFtPm4V8qFV5v v1Sg== X-Gm-Message-State: AOJu0Yy7QrcMSdMWA8azRWvCZdvhvBNlEHDmXSgXaxVjYtH8i2vjLgdT ONXCoLzeQje5wqIXTZL0+M4ZOD3p6ZQyyIUnwcs749n2H/Y= X-Google-Smtp-Source: AGHT+IGGiBc3aZZZA5aurfolZP5L5u2bbef1yv0+fPOJp3vJEMFZHifDUVa9r7947LiLkpiyT25ceg== X-Received: by 2002:adf:e989:0:b0:336:d299:ada5 with SMTP id h9-20020adfe989000000b00336d299ada5mr482341wrm.112.1704971111723; Thu, 11 Jan 2024 03:05:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/41] target/arm: Implement HCR_EL2.AT handling Date: Thu, 11 Jan 2024 11:04:35 +0000 Message-Id: <20240111110505.1563291-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240111110505.1563291-1-peter.maydell@linaro.org> References: <20240111110505.1563291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704971180174100004 Content-Type: text/plain; charset="utf-8" The FEAT_NV HCR_EL2.AT bit enables trapping of some address translation instructions from EL1 to EL2. Implement this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Tested-by: Miguel Luis --- target/arm/helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4e5fd25199c..dc4b4123e00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3703,6 +3703,15 @@ static CPAccessResult at_s1e2_access(CPUARMState *en= v, const ARMCPRegInfo *ri, return at_e012_access(env, ri, isread); } =20 +static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_AT)) { + return CP_ACCESS_TRAP_EL2; + } + return at_e012_access(env, ri, isread); +} + static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5568,22 +5577,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1R, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1W, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E0R, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E0W, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, @@ -8168,12 +8177,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1RP, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1WP, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, }; =20 static const ARMCPRegInfo ats1cp_reginfo[] =3D { --=20 2.34.1