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([172.58.27.160]) by smtp.gmail.com with ESMTPSA id ks23-20020ac86217000000b0042987f6874bsm2092281qtb.92.2024.01.10.14.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 14:46:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704926800; x=1705531600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3V+CWkXdNqNJeKthv/lyY08kBwUymIwSbvahoKExcsA=; b=sgQcaqVDhrxnO4ZeTdfSaIJMdKeX46Fd6pjNoYtaS4wEuUtAzg8VLlzyUkBpIgLslL LQwx7pmB6u4Lee5DNroQx7jSsxIu8MjhEMxyr7RZyLEJGzBMOV9RcDMtNgi7zQfM8nea jIf0LMsMOOAmTWyN0d6CG0b3r8qEOumg4s8VpEKK58+MNmjQINOHaBiqQrvl8ay52EcT NQ4nVV8aZ6wULoOLN90iDUoXzvC1GmKUzVJdH8xQnnHr9POjn9LiT8Q3xAvXeAy3f1gF t3MbHEUoreOceIZubKqEwFLPgD4yRBj/JPT7xg7vak8TnOsJN/txBrawFx4uoLKSAdhc mzSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704926800; x=1705531600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3V+CWkXdNqNJeKthv/lyY08kBwUymIwSbvahoKExcsA=; b=RGtXSXtR9D2EEKn7dMRrMI9uRGCOcx6jtL20uaO0JmpLcynFuX13CW9M6bcsSzdoIa ZXRv3EeOTgdE6pdTHCn3Quu3pEvGsPqfefHWO/c+IJzBuC2p1gbrBmNYBnPO1C91MySp SMjb8T7fKY/kRjwAcDSfEINzT/ms1d4T3rH4+++jOSUKT+3gr94nkMq+FEZJ7TiNyOB1 F7pVnLEoMB3+h4yykmRJUATbKNaBKEguMXxAbT6WihG19uBo9sxPrqppccBhcAwljj8/ zkHSGR6WJxRYRrR/O+G78o/ZwcheeeTW+EZkLgKSK48OzZQfmL+C7FiQd4/BSV5oypGu Ni1g== X-Gm-Message-State: AOJu0Yxmk004Sjib7gPqAMXEwCeyGAFaRjtJjrn1Aj6j0+U0FfRqHlzO +aO2UoV0bgVHlM7/ybHp+mgz5qH6xpNIejucXsn10QNki1sKUXFb X-Google-Smtp-Source: AGHT+IG0fIUOVCiiihf4C5V64lNv4+G3gjUkv4eCGiuPu1fr942xbmfATaMIOulXSGuI9X9NL0P/vA== X-Received: by 2002:a05:622a:110:b0:429:c15c:7d91 with SMTP id u16-20020a05622a011000b00429c15c7d91mr27654qtw.137.1704926800705; Wed, 10 Jan 2024 14:46:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Date: Thu, 11 Jan 2024 09:44:01 +1100 Message-Id: <20240110224408.10444-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110224408.10444-1-richard.henderson@linaro.org> References: <20240110224408.10444-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::833; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x833.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704926869452100001 Content-Type: text/plain; charset="utf-8" Using cr0 means we could choose to use rc=3D1 to compute the condition. Adjust the tables and tcg_out_cmp that feeds them. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/ppc/tcg-target.c.inc | 68 ++++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 830d2fe73a..b9323baa86 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -671,30 +671,30 @@ enum { }; =20 static const uint32_t tcg_to_bc[] =3D { - [TCG_COND_EQ] =3D BC | BI(7, CR_EQ) | BO_COND_TRUE, - [TCG_COND_NE] =3D BC | BI(7, CR_EQ) | BO_COND_FALSE, - [TCG_COND_LT] =3D BC | BI(7, CR_LT) | BO_COND_TRUE, - [TCG_COND_GE] =3D BC | BI(7, CR_LT) | BO_COND_FALSE, - [TCG_COND_LE] =3D BC | BI(7, CR_GT) | BO_COND_FALSE, - [TCG_COND_GT] =3D BC | BI(7, CR_GT) | BO_COND_TRUE, - [TCG_COND_LTU] =3D BC | BI(7, CR_LT) | BO_COND_TRUE, - [TCG_COND_GEU] =3D BC | BI(7, CR_LT) | BO_COND_FALSE, - [TCG_COND_LEU] =3D BC | BI(7, CR_GT) | BO_COND_FALSE, - [TCG_COND_GTU] =3D BC | BI(7, CR_GT) | BO_COND_TRUE, + [TCG_COND_EQ] =3D BC | BI(0, CR_EQ) | BO_COND_TRUE, + [TCG_COND_NE] =3D BC | BI(0, CR_EQ) | BO_COND_FALSE, + [TCG_COND_LT] =3D BC | BI(0, CR_LT) | BO_COND_TRUE, + [TCG_COND_GE] =3D BC | BI(0, CR_LT) | BO_COND_FALSE, + [TCG_COND_LE] =3D BC | BI(0, CR_GT) | BO_COND_FALSE, + [TCG_COND_GT] =3D BC | BI(0, CR_GT) | BO_COND_TRUE, + [TCG_COND_LTU] =3D BC | BI(0, CR_LT) | BO_COND_TRUE, + [TCG_COND_GEU] =3D BC | BI(0, CR_LT) | BO_COND_FALSE, + [TCG_COND_LEU] =3D BC | BI(0, CR_GT) | BO_COND_FALSE, + [TCG_COND_GTU] =3D BC | BI(0, CR_GT) | BO_COND_TRUE, }; =20 /* The low bit here is set if the RA and RB fields must be inverted. */ static const uint32_t tcg_to_isel[] =3D { - [TCG_COND_EQ] =3D ISEL | BC_(7, CR_EQ), - [TCG_COND_NE] =3D ISEL | BC_(7, CR_EQ) | 1, - [TCG_COND_LT] =3D ISEL | BC_(7, CR_LT), - [TCG_COND_GE] =3D ISEL | BC_(7, CR_LT) | 1, - [TCG_COND_LE] =3D ISEL | BC_(7, CR_GT) | 1, - [TCG_COND_GT] =3D ISEL | BC_(7, CR_GT), - [TCG_COND_LTU] =3D ISEL | BC_(7, CR_LT), - [TCG_COND_GEU] =3D ISEL | BC_(7, CR_LT) | 1, - [TCG_COND_LEU] =3D ISEL | BC_(7, CR_GT) | 1, - [TCG_COND_GTU] =3D ISEL | BC_(7, CR_GT), + [TCG_COND_EQ] =3D ISEL | BC_(0, CR_EQ), + [TCG_COND_NE] =3D ISEL | BC_(0, CR_EQ) | 1, + [TCG_COND_LT] =3D ISEL | BC_(0, CR_LT), + [TCG_COND_GE] =3D ISEL | BC_(0, CR_LT) | 1, + [TCG_COND_LE] =3D ISEL | BC_(0, CR_GT) | 1, + [TCG_COND_GT] =3D ISEL | BC_(0, CR_GT), + [TCG_COND_LTU] =3D ISEL | BC_(0, CR_LT), + [TCG_COND_GEU] =3D ISEL | BC_(0, CR_LT) | 1, + [TCG_COND_LEU] =3D ISEL | BC_(0, CR_GT) | 1, + [TCG_COND_GTU] =3D ISEL | BC_(0, CR_GT), }; =20 static bool patch_reloc(tcg_insn_unit *code_ptr, int type, @@ -1827,7 +1827,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, if (have_isa_3_10) { tcg_insn_unit bi, opc; =20 - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); =20 /* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */ bi =3D tcg_to_bc[cond] & (0x1f << 16); @@ -1880,7 +1880,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, if (have_isel) { int isel, tab; =20 - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); =20 isel =3D tcg_to_isel[cond]; =20 @@ -1966,7 +1966,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond con= d, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *l, TCGType type) { - tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); tcg_out_bc_lab(s, cond, l); } =20 @@ -1980,7 +1980,7 @@ static void tcg_out_movcond(TCGContext *s, TCGType ty= pe, TCGCond cond, return; } =20 - tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); + tcg_out_cmp(s, cond, c1, c2, const_c2, 0, type); =20 if (have_isel) { int isel =3D tcg_to_isel[cond]; @@ -2024,7 +2024,7 @@ static void tcg_out_cntxz(TCGContext *s, TCGType type= , uint32_t opc, if (const_a2 && a2 =3D=3D (type =3D=3D TCG_TYPE_I32 ? 32 : 64)) { tcg_out32(s, opc | RA(a0) | RS(a1)); } else { - tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); + tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 0, type); /* Note that the only other valid constant for a2 is 0. */ if (have_isel) { tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); @@ -2079,7 +2079,7 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg = *args, do_equality: tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); break; =20 case TCG_COND_LT: @@ -2097,8 +2097,8 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg = *args, =20 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); - tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); - tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); + tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); + tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ)); break; =20 default: @@ -2110,8 +2110,8 @@ static void tcg_out_setcond2(TCGContext *s, const TCG= Arg *args, const int *const_args) { tcg_out_cmp2(s, args + 1, const_args + 1); - tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); - tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); + tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0)); + tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31); } =20 static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, @@ -2442,12 +2442,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32); =20 - /* Combine comparisons into cr7. */ - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ= )); + /* Combine comparisons into cr0. */ + tcg_out32(s, CRAND | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ= )); } else { - /* Full comparison into cr7. */ + /* Full comparison into cr0. */ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, - 0, 7, addr_type); + 0, 0, addr_type); } =20 /* Load a pointer into the current opcode w/conditional branch-lin= k. */ --=20 2.34.1