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([172.58.27.160]) by smtp.gmail.com with ESMTPSA id ks23-20020ac86217000000b0042987f6874bsm2092281qtb.92.2024.01.10.14.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 14:44:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704926676; x=1705531476; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XHALRgn6+R7mnoPisAPyxnrzriWZt0G/V66nE0399oE=; b=BlwGvnoNSNq7Ud7H9aO2FbiPhE3viZ1+CdtNj3/3i49OogrWH9BH9sPlRXaFr2+Rr+ DezhlBHXH3EYYXHL0IKwCmhRVpIV7cBJiPKLiffdaFRe3E1jcttbn5GYcClyXNU89Eaf TNXmHumbXgAt7QUaYItNRf3vfV29FCscCEFW/d7E/KUvtmB9Cv5kpoxeTcpnKaWHAY/I EAn2vSSX/Zo9oqTvbyQjgpiDHFvaNEaPbRpEMvy1vhx1lUenalBkCnXA/SjgDPi8zYHh vF4HMzH7FgxEAqi2w2LBqouYXr4MHZcw2aTMjnIRzXqa3L5MnDslZPA2U3nfuVww4AwK AzUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704926676; x=1705531476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XHALRgn6+R7mnoPisAPyxnrzriWZt0G/V66nE0399oE=; b=Ilpz/ZgqCb/xdFw2mhnxr7RokofsoC66KLfjsoZYOzLOUK4mm+DIQNmGkz5DbDB4/u 5QOmGL98hGH8Rf7SR63cYV/TigF0tQmI+Qu9E4ldqLVw/Yh6ElHUtHOyygKjmjNpSK++ 5cgudcXctaGyZFSL4hTS0TKCZ/wTLaq2ripXaCzXeovQqdcQcXpuMoNCAYXyErKHaEZO CQmDKrCWXvjKgx88MHEGxTsj0iqm+8Ngg8apS9pzYixeVcSrClnma7K71m2fz7cylnk8 9sZ/4/QbJLt83YUMDnzk6zOjfmWhLJ+hvI011KK5zARyGjhjUKyGeDhuUTWPXjPIydyZ 0jjw== X-Gm-Message-State: AOJu0YzBDo7VB7UU7YVSl0WDhXB+gj2prM24lXXZgaCtERcSyclBeM6M 5jid02v4PDx33Zdzy6akHbHqj4w+PUXh8jU78jrh4n49rcZdqej1 X-Google-Smtp-Source: AGHT+IGqwBR2ufQFZs0dLeb4G5GUCLJoGZMrhIxw/nOkCCTai9IV39Ju7YAZit1+nPAHh1P1MvZUqA== X-Received: by 2002:a05:622a:1a90:b0:429:b349:65a7 with SMTP id s16-20020a05622a1a9000b00429b34965a7mr396023qtc.8.1704926676671; Wed, 10 Jan 2024 14:44:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v3 02/38] tcg: Introduce TCG_TARGET_HAS_tst Date: Thu, 11 Jan 2024 09:43:32 +1100 Message-Id: <20240110224408.10444-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110224408.10444-1-richard.henderson@linaro.org> References: <20240110224408.10444-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82c; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704926853378100018 Content-Type: text/plain; charset="utf-8" Define as 0 for all tcg backends. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 2 ++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tci/tcg-target.h | 2 ++ 10 files changed, 20 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 33f15a564a..b4ac13be7b 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -138,6 +138,8 @@ typedef enum { #define TCG_TARGET_HAS_qemu_ldst_i128 1 #endif =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_TARGET_HAS_v64 1 #define TCG_TARGET_HAS_v128 1 #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index a712cc80ad..7bf42045a7 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -125,6 +125,8 @@ extern bool use_neon_instructions; =20 #define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_TARGET_HAS_v64 use_neon_instructions #define TCG_TARGET_HAS_v128 use_neon_instructions #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index fa34deec47..1dd917a680 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -198,6 +198,8 @@ typedef enum { #define TCG_TARGET_HAS_qemu_ldst_i128 \ (TCG_TARGET_REG_BITS =3D=3D 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA)) =20 +#define TCG_TARGET_HAS_tst 0 + /* We do not support older SSE systems, only beginning with AVX1. */ #define TCG_TARGET_HAS_v64 have_avx1 #define TCG_TARGET_HAS_v128 have_avx1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 9c70ebfefc..fede627bf7 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -169,6 +169,8 @@ typedef enum { =20 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_TARGET_HAS_v64 0 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index b98ffae1d0..a996aa171d 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -194,6 +194,8 @@ extern bool use_mips32r2_instructions; =20 #define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_TARGET_DEFAULT_MO 0 #define TCG_TARGET_NEED_LDST_LABELS #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5295e4f9ab..60ce49e672 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -143,6 +143,8 @@ typedef enum { #define TCG_TARGET_HAS_qemu_ldst_i128 \ (TCG_TARGET_REG_BITS =3D=3D 64 && have_isa_2_07) =20 +#define TCG_TARGET_HAS_tst 0 + /* * While technically Altivec could support V64, it has no 64-bit store * instruction and substituting two 32-bit stores makes the generated diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index a4edc3dc74..2c1b680b93 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -158,6 +158,8 @@ extern bool have_zbb; =20 #define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_TARGET_DEFAULT_MO (0) =20 #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e69b0d2ddd..53bed8c8d2 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -138,6 +138,8 @@ extern uint64_t s390_facilities[3]; =20 #define TCG_TARGET_HAS_qemu_ldst_i128 1 =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index f8cf145266..ae2910c4ee 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -149,6 +149,8 @@ extern bool use_vis3_instructions; =20 #define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 +#define TCG_TARGET_HAS_tst 0 + #define TCG_AREG0 TCG_REG_I0 =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 2a13816c8e..609b2f4e4a 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -117,6 +117,8 @@ =20 #define TCG_TARGET_HAS_qemu_ldst_i128 0 =20 +#define TCG_TARGET_HAS_tst 0 + /* Number of registers available. */ #define TCG_TARGET_NB_REGS 16 =20 --=20 2.34.1