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([172.58.27.160]) by smtp.gmail.com with ESMTPSA id z8-20020ae9c108000000b0078313c87609sm1888387qki.100.2024.01.10.13.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 13:52:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704923543; x=1705528343; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HwFKj5Pn5DjJGhI9eC5OFFV9tA3PvMraO52aS5I9wUY=; b=rridXl3+jdqbF7VGMLtTvQ0Yonrw6h4zHrKsfStlGzXFX6sEwUTCAfQgE9tzC1L3zR O6KqHRBVmJhBUJu8Stu5ijr+ZNz8iX3+SpnCFWq4Wa4eeY+SD0GAPIuqsGQMda0ZtoSA HzJGmi65fSLsid8JG60XuFZlBBug4qrGjXkicsWcEbTlxVY9W7rfkjzD6uzHaibOVBUe Iat3Cv/G+Ns1dP997/ieLu8h11puMVU0qrFLT0QJd9cVbUg1rUWxyKlcSjnIHQoZE3cg mgGYlhWqsxhIh37L+vJDq6e5UikkHrWvP8rgCFfjstDTuKuC77FhiSRCRonHmW8VMi40 HxUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704923543; x=1705528343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HwFKj5Pn5DjJGhI9eC5OFFV9tA3PvMraO52aS5I9wUY=; b=RgFo+qekcviHHeyhGD0GHO0e6rmxC5I+SJHzSqybKbH7Z2EhGzZuAP835lZdCoSRkY ultOkPQJO0qlmWLZ81HtgZf1Y0DTwvI2SSnUo1QsCsz6Zj0mD+K3ImJ0ExPSlpVn0pBR mA6VPBqBWyzbeWvR0p8BPRGzBRSxAGCUi2IHiPVN82E79wfp5lDwcOGz7J2UpXMFUCV8 Yu/Dei+zx4YoJjZbIFsvbdSgq38dn6s406A2fL8oH8h3qc/P4nutNmMWlJ8c3B2fLVWI WcaIjbp6wC7MUpRKxIliXk/v97mQ4nsmTTcNRt1ghKGy2UR/dyZmMsqplHf3PkQWICSn pk1A== X-Gm-Message-State: AOJu0YwPFDksURV+Oxiqm3IlYZ90wxM1CeCPyRPiXpJ0XE3aIfauf+aZ 33+05fVPv2lQfPg108ZcFWgbqEKFiZzxPHi2K03VDY9DrW5RhPYJ X-Google-Smtp-Source: AGHT+IEb9FewlU6zcIzwO9ISoe8I6qtl57Oil2dp63eCvwjrzbtHHrlPxqzDEVyCc16TzBh0lYgeEg== X-Received: by 2002:a05:620a:3914:b0:783:2a6a:7b82 with SMTP id qr20-20020a05620a391400b007832a6a7b82mr388836qkn.98.1704923542755; Wed, 10 Jan 2024 13:52:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 3/4] tcg/ppc: Use new registers for LQ destination Date: Thu, 11 Jan 2024 08:52:03 +1100 Message-Id: <20240110215204.9353-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110215204.9353-1-richard.henderson@linaro.org> References: <20240110215204.9353-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::734; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x734.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704923615063100003 LQ has a constraint that RTp !=3D RA, else SIGILL. Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a new register pair, so that it cannot overlap the input address. This requires new support in process_op_defs and tcg_reg_alloc_op. Cc: qemu-stable@nongnu.org Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org> Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 2 +- tcg/tcg.c | 21 ++++++++++++++++----- tcg/ppc/tcg-target.c.inc | 3 ++- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index bbd7b21247..cb47b29452 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -35,7 +35,7 @@ C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) C_O2_I1(r, r, r) -C_O2_I1(o, m, r) +C_N1O1_I1(o, m, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/tcg.c b/tcg/tcg.c index 896a36caeb..e2c38f6d11 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -653,6 +653,7 @@ static void tcg_out_movext3(TCGContext *s, const TCGMov= Extend *i1, #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I= 4), =20 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), +#define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1), #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1), =20 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), @@ -676,6 +677,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e); #undef C_O1_I3 #undef C_O1_I4 #undef C_N1_I2 +#undef C_N1O1_I1 #undef C_N2_I1 #undef C_O2_I1 #undef C_O2_I2 @@ -696,6 +698,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e); #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str =3D { #O1, #I1, #I2= , #I3, #I4 } }, =20 #define C_N1_I2(O1, I1, I2) { .args_ct_str =3D { "&" #O1, #I1,= #I2 } }, +#define C_N1O1_I1(O1, O2, I1) { .args_ct_str =3D { "&" #O1, #O2,= #I1 } }, #define C_N2_I1(O1, O2, I1) { .args_ct_str =3D { "&" #O1, "&" = #O2, #I1 } }, =20 #define C_O2_I1(O1, O2, I1) { .args_ct_str =3D { #O1, #O2, #I1= } }, @@ -718,6 +721,7 @@ static const TCGTargetOpDef constraint_sets[] =3D { #undef C_O1_I3 #undef C_O1_I4 #undef C_N1_I2 +#undef C_N1O1_I1 #undef C_N2_I1 #undef C_O2_I1 #undef C_O2_I2 @@ -738,6 +742,7 @@ static const TCGTargetOpDef constraint_sets[] =3D { #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I= 4) =20 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) +#define C_N1O1_I1(O1, O2, I1) C_PFX3(c_n1o1_i1_, O1, O2, I1) #define C_N2_I1(O1, O2, I1) C_PFX3(c_n2_i1_, O1, O2, I1) =20 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) @@ -2988,6 +2993,7 @@ static void process_op_defs(TCGContext *s) .pair =3D 2, .pair_index =3D o, .regs =3D def->args_ct[o].regs << 1, + .newreg =3D def->args_ct[o].newreg, }; def->args_ct[o].pair =3D 1; def->args_ct[o].pair_index =3D i; @@ -3004,6 +3010,7 @@ static void process_op_defs(TCGContext *s) .pair =3D 1, .pair_index =3D o, .regs =3D def->args_ct[o].regs >> 1, + .newreg =3D def->args_ct[o].newreg, }; def->args_ct[o].pair =3D 2; def->args_ct[o].pair_index =3D i; @@ -5036,17 +5043,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) break; =20 case 1: /* first of pair */ - tcg_debug_assert(!arg_ct->newreg); if (arg_ct->oalias) { reg =3D new_args[arg_ct->alias_index]; - break; + } else if (arg_ct->newreg) { + reg =3D tcg_reg_alloc_pair(s, arg_ct->regs, + i_allocated_regs | o_allocate= d_regs, + output_pref(op, k), + ts->indirect_base); + } else { + reg =3D tcg_reg_alloc_pair(s, arg_ct->regs, o_allocate= d_regs, + output_pref(op, k), + ts->indirect_base); } - reg =3D tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_re= gs, - output_pref(op, k), ts->indirect_= base); break; =20 case 2: /* second of pair */ - tcg_debug_assert(!arg_ct->newreg); if (arg_ct->oalias) { reg =3D new_args[arg_ct->alias_index]; } else { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 856c3b18f5..54816967bc 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2595,6 +2595,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCG= Reg datalo, TCGReg datahi, tcg_debug_assert(!need_bswap); tcg_debug_assert(datalo & 1); tcg_debug_assert(datahi =3D=3D datalo - 1); + tcg_debug_assert(!is_ld || datahi !=3D index); insn =3D is_ld ? LQ : STQ; tcg_out32(s, insn | TAI(datahi, index, 0)); } else { @@ -4071,7 +4072,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) =20 case INDEX_op_qemu_ld_a32_i128: case INDEX_op_qemu_ld_a64_i128: - return C_O2_I1(o, m, r); + return C_N1O1_I1(o, m, r); case INDEX_op_qemu_st_a32_i128: case INDEX_op_qemu_st_a64_i128: return C_O0_I3(o, m, r); --=20 2.34.1