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charset="utf-8" It's possible for a reset to come in the middle of a transaction, which causes the bus to be in an old state when a new transaction comes in. Signed-off-by: Joe Komlodi --- hw/i2c/core.c | 30 +++++++++++++++++++++++++----- include/hw/i2c/i2c.h | 6 +++++- 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/hw/i2c/core.c b/hw/i2c/core.c index 4cf30b2c86..def4f134d0 100644 --- a/hw/i2c/core.c +++ b/hw/i2c/core.c @@ -23,11 +23,31 @@ static Property i2c_props[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static const TypeInfo i2c_bus_info =3D { - .name =3D TYPE_I2C_BUS, - .parent =3D TYPE_BUS, - .instance_size =3D sizeof(I2CBus), -}; +static void i2c_bus_enter_reset(Object *obj, ResetType type) +{ + I2CBus *bus =3D I2C_BUS(obj); + I2CNode *node, *next; + + bus->broadcast =3D false; + QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) { + QLIST_REMOVE(node, next); + g_free(node); + } +} + +static void i2c_bus_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D i2c_bus_enter_reset; +} + + static const TypeInfo i2c_bus_info =3D { + .name =3D TYPE_I2C_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(I2CBus), + .class_size =3D sizeof(I2CBusClass), + .class_init =3D i2c_bus_class_init, + }; =20 static int i2c_bus_pre_save(void *opaque) { diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h index 2a3abacd1b..420868a269 100644 --- a/include/hw/i2c/i2c.h +++ b/include/hw/i2c/i2c.h @@ -64,7 +64,7 @@ struct I2CSlave { }; =20 #define TYPE_I2C_BUS "i2c-bus" -OBJECT_DECLARE_SIMPLE_TYPE(I2CBus, I2C_BUS) +OBJECT_DECLARE_TYPE(I2CBus, I2CBusClass, I2C_BUS) =20 typedef struct I2CNode I2CNode; =20 @@ -83,6 +83,10 @@ struct I2CPendingMaster { typedef QLIST_HEAD(I2CNodeList, I2CNode) I2CNodeList; typedef QSIMPLEQ_HEAD(I2CPendingMasters, I2CPendingMaster) I2CPendingMaste= rs; =20 +struct I2CBusClass { + DeviceClass parent_class; +}; + struct I2CBus { BusState qbus; I2CNodeList current_devs; --=20 2.43.0.472.g3155946c3a-goog From nobody Sun Nov 10 21:51:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" The current logging doesn't tell us which specific smbus device is an error state. Signed-off-by: Joe Komlodi --- hw/i2c/smbus_slave.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c index 1300c9ec72..e24a1ef472 100644 --- a/hw/i2c/smbus_slave.c +++ b/hw/i2c/smbus_slave.c @@ -25,11 +25,15 @@ #define DPRINTF(fmt, ...) \ do { printf("smbus(%02x): " fmt , dev->i2c.address, ## __VA_ARGS__); } whi= le (0) #define BADF(fmt, ...) \ -do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__); exit(1);} whi= le (0) +do { fprintf(stderr, "%s: smbus: error: " fmt , \ + object_get_canonical_path(OBJECT(dev)), ## __VA_ARGS__); \ + exit(1); } while (0) #else #define DPRINTF(fmt, ...) do {} while(0) #define BADF(fmt, ...) \ -do { fprintf(stderr, "smbus: error: " fmt , ## __VA_ARGS__);} while (0) +do { fprintf(stderr, "%s: smbus: error: " fmt , \ + object_get_canonical_path(OBJECT(dev)), ## __VA_ARGS__); \ + } while (0) #endif =20 enum { --=20 2.43.0.472.g3155946c3a-goog From nobody Sun Nov 10 21:51:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" If a reset comes while the SMBus device is not in its idle state, it's possible for it to get confused on valid transactions post-reset. Signed-off-by: Joe Komlodi --- hw/i2c/smbus_slave.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c index e24a1ef472..58abde29de 100644 --- a/hw/i2c/smbus_slave.c +++ b/hw/i2c/smbus_slave.c @@ -201,10 +201,19 @@ static int smbus_i2c_send(I2CSlave *s, uint8_t data) return 0; } =20 +static void smbus_device_enter_reset(Object *obj, ResetType type) +{ + SMBusDevice *dev =3D SMBUS_DEVICE(obj); + dev->mode =3D SMBUS_IDLE; + dev->data_len =3D 0; +} + static void smbus_device_class_init(ObjectClass *klass, void *data) { I2CSlaveClass *sc =3D I2C_SLAVE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 + rc->phases.enter =3D smbus_device_enter_reset; sc->event =3D smbus_i2c_event; sc->recv =3D smbus_i2c_recv; sc->send =3D smbus_i2c_send; --=20 2.43.0.472.g3155946c3a-goog From nobody Sun Nov 10 21:51:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" When a reset happens, both the SMBusDevice and PCA954x class do their variable resetting on an enter reset. Because of this, only the PCA954x has its reset called, which can leave the SMBusDevice in a bad state if it was in the middle of a transaction. To fix this we add parent reset functions for the SMBusDevice class, and have the mux class invoke it when it resets. Signed-off-by: Joe Komlodi --- hw/i2c/i2c_mux_pca954x.c | 5 +++++ hw/i2c/smbus_slave.c | 3 +++ include/hw/i2c/smbus_slave.h | 1 + 3 files changed, 9 insertions(+) diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c index db5db956a6..307359a518 100644 --- a/hw/i2c/i2c_mux_pca954x.c +++ b/hw/i2c/i2c_mux_pca954x.c @@ -159,8 +159,13 @@ static uint8_t pca954x_read_byte(SMBusDevice *d) static void pca954x_enter_reset(Object *obj, ResetType type) { Pca954xState *s =3D PCA954X(obj); + Pca954xClass *pc =3D PCA954X_GET_CLASS(obj); + /* Reset will disable all channels. */ pca954x_write(s, 0); + if (pc->parent.parent_phases.enter) { + pc->parent.parent_phases.enter(obj, type); + } } =20 I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel) diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c index 58abde29de..81adab8f77 100644 --- a/hw/i2c/smbus_slave.c +++ b/hw/i2c/smbus_slave.c @@ -212,8 +212,11 @@ static void smbus_device_class_init(ObjectClass *klass= , void *data) { I2CSlaveClass *sc =3D I2C_SLAVE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); + SMBusDeviceClass *sdc =3D SMBUS_DEVICE_CLASS(klass); =20 rc->phases.enter =3D smbus_device_enter_reset; + resettable_class_set_parent_phases(rc, smbus_device_enter_reset, NULL,= NULL, + &sdc->parent_phases); sc->event =3D smbus_i2c_event; sc->recv =3D smbus_i2c_recv; sc->send =3D smbus_i2c_send; diff --git a/include/hw/i2c/smbus_slave.h b/include/hw/i2c/smbus_slave.h index 86bfe0a79e..0dd14be178 100644 --- a/include/hw/i2c/smbus_slave.h +++ b/include/hw/i2c/smbus_slave.h @@ -35,6 +35,7 @@ OBJECT_DECLARE_TYPE(SMBusDevice, SMBusDeviceClass, =20 struct SMBusDeviceClass { I2CSlaveClass parent_class; + ResettablePhases parent_phases; =20 /* * An operation with no data, special in SMBus. --=20 2.43.0.472.g3155946c3a-goog