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Iglesias" , Leif Lindholm , Rob Herring , Markus Armbruster , Alistair Francis , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 01/14] hw/arm/armv7m: Introduce cpudev variable in armv7m_realize() Date: Wed, 10 Jan 2024 20:53:15 +0100 Message-ID: <20240110195329.3995-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240110195329.3995-1-philmd@linaro.org> References: <20240110195329.3995-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1704916479960100009 We are going to cast s->cpu as DeviceState multiple times. Add a local 'cpudev' variable to simplify code review, having a single DEVICE(s->cpu) conversion. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/arm/armv7m.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 50c6c6b1f5..d239468558 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -277,6 +277,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) { ARMv7MState *s =3D ARMV7M(dev); SysBusDevice *sbd; + DeviceState *cpudev; Error *err =3D NULL; int i; =20 @@ -299,6 +300,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) error_propagate(errp, err); return; } + cpudev =3D DEVICE(s->cpu); =20 object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->containe= r), &error_abort); @@ -356,7 +358,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) s->cpu->env.nvic =3D &s->nvic; s->nvic.cpu =3D s->cpu; =20 - if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { + if (!qdev_realize(cpudev, NULL, errp)) { return; } =20 @@ -426,8 +428,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) =20 /* Wire the NVIC up to the CPU */ sbd =3D SYS_BUS_DEVICE(&s->nvic); - sysbus_connect_irq(sbd, 0, - qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); =20 memory_region_add_subregion(&s->container, 0xe000e000, sysbus_mmio_get_region(sbd, 0)); --=20 2.41.0