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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.01.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 01:01:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877288; x=1705482088; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/1I0SyhcsXN3UdWgUzk4g0SlxxbZqG+MteFeWCN3sU4=; b=C0ihVK3M2ySj0LAs0IN97wipDIH62z1IUwz+ys8UIJ+4YkyFhnvGxGdJ2osuEX+uF4 VuBGHEO4eCcGXB0y0RO+dkR+2hCjgiFczSz//SO/oIyTSe+Fy8Bm2NGJ6tbi6QDThVFB NrM7t6QcZSCw1Uu6fYsDUZP5IRSqCWnah0ej54cNOF933fe2GvspNxK8+1yZHjtRWSxO v/qV+pgML5crj2Br1uHAYhgcRzeGcuOw7t72yEdVhJl4gdTHfcXRbRyszKkKILBgcQ4E 65bV/kqHjZ0yMqyjTcZZPiFrYUPEv3E4l07HCnmUTbtYahl+w69Eg0/jlyfpd8/lkU2l fSaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877288; x=1705482088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/1I0SyhcsXN3UdWgUzk4g0SlxxbZqG+MteFeWCN3sU4=; b=e2JVN9AoFRfVSmA2oMiWIPe2ERw2XuwSDPY61ArMINid4LRoHS6x18Zn1YuxtIbHSV CRcoE3JBnk3TqSJIPUNQ15OS576Nj85sdfRxs+HG9ZBjomah4/uctadM2wnfls9okT9z xTVInAu8PycuPAQXOAQ46Zg4Bu1TjoHOefWukZV34O4CpJmbLYRTpy4aMyplN2NR9eRJ MVaM7/Lt/UXbv8mII3k37mOCFltbWGXBjR6UZc/Jj3iNnCSVaM7+6CvyBZutjt/xoBD7 +V4J+flvXKgNvDj3x/94f5ElxlwldZok9Sid+BltPCpFee1fydwRs6ZugJTgmWu8zoMK 8iTQ== X-Gm-Message-State: AOJu0YzWRnsRTnUMAUgg1C5RqtHftjuOgvt3JI6RZcUek/dlGJNUtR9O 7ayy3SYiTqVK5D3kSBtiNr/Ey2ab484mUI9Q X-Google-Smtp-Source: AGHT+IH6CifiNdLxleROCebTwcDVcPlExJWH88TimN+kUPY5gvqlaM+WU5qnm06AFI2FC/Y67AFHCQ== X-Received: by 2002:a9d:7a4d:0:b0:6dd:e215:4605 with SMTP id z13-20020a9d7a4d000000b006dde2154605mr267560otm.6.1704877288428; Wed, 10 Jan 2024 01:01:28 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL 59/65] target/riscv/kvm: add RVV and Vector CSR regs Date: Wed, 10 Jan 2024 18:57:27 +1000 Message-ID: <20240110085733.1607526-60-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=alistair23@gmail.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877610736100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add support for RVV and Vector CSR KVM regs vstart, vl and vtype. Support for vregs[] requires KVM side changes and an extra reg (vlenb) and will be added later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20231218204321.75757-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 74 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index d7d6fb1af0..680a729cd8 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -105,6 +105,10 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, ui= nt64_t idx) =20 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) =20 +#define RISCV_VECTOR_CSR_REG(env, name) \ + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ + KVM_REG_RISCV_VECTOR_CSR_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ @@ -158,6 +162,7 @@ static KVMCPUConfig kvm_misa_ext_cfgs[] =3D { KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), + KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), }; =20 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, @@ -709,6 +714,65 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) env->kvm_timer_dirty =3D false; } =20 +static int kvm_riscv_get_regs_vector(CPUState *cs) +{ + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + target_ulong reg; + int ret =3D 0; + + if (!riscv_has_ext(env, RVV)) { + return 0; + } + + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + if (ret) { + return ret; + } + env->vstart =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + if (ret) { + return ret; + } + env->vl =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + if (ret) { + return ret; + } + env->vtype =3D reg; + + return 0; +} + +static int kvm_riscv_put_regs_vector(CPUState *cs) +{ + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + target_ulong reg; + int ret =3D 0; + + if (!riscv_has_ext(env, RVV)) { + return 0; + } + + reg =3D env->vstart; + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + if (ret) { + return ret; + } + + reg =3D env->vl; + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + if (ret) { + return ret; + } + + reg =3D env->vtype; + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + + return ret; +} + typedef struct KVMScratchCPU { int kvmfd; int vmfd; @@ -1004,6 +1068,11 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 + ret =3D kvm_riscv_get_regs_vector(cs); + if (ret) { + return ret; + } + return ret; } =20 @@ -1044,6 +1113,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 + ret =3D kvm_riscv_put_regs_vector(cs); + if (ret) { + return ret; + } + if (KVM_PUT_RESET_STATE =3D=3D level) { RISCVCPU *cpu =3D RISCV_CPU(cs); if (cs->cpu_index =3D=3D 0) { --=20 2.43.0