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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.01.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 01:01:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877270; x=1705482070; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=98U4oU6QyYIjFXPReF2BbuPWqRX5URTGZmXI6rweO/Y=; b=QF6Z+VlQPdIkTafggLJpn4sd7CwCuXWSHEVKlzapEVNJkMz4glAdafIbegiDHbEwxr tUBlabbXcrIyNV6oQX3MHrfkZeSpEvU0IKdcLRKpnVpBEmEgg6jxa2O6TnNK9ieGIhQt oMGT0zgZW5WPScpEl/Am4N4nWnMNOfoSkkjoqtQEzIUmRA9oA2bQj3ee5/pJ/iNNivF8 m+ySgFw+RdFDj2Sy1zJCyg4nBrIUZGM/n88/BAQacGLVrciT6F9pgSQKd7odvntEvG9e Wm1aDcFNSv4Zdc5E7iuuXzsRv5ylsPlVw6J8pSrZJOD1WHg7PbKHJ64p6+t6shKUBSPJ 9O9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877270; x=1705482070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=98U4oU6QyYIjFXPReF2BbuPWqRX5URTGZmXI6rweO/Y=; b=Y4H/q4Jk0RfuZKFbvqEtwLM7dETF7NMLr5fQgqLHcldVQwrjNsWbT+tmsiggpbX9lg cg3MIhnwfnQ/YvYHT14Bd+bS9YNL+VPYW9j5nb2UrZVL15nN1GUT220CKPK9bfvd5Eb9 OGasu/bV1uRV6ZKP79rJERS8Fk6fDtEUXBTPJ/rPyS2+N+PN8IVAzykz0zccDhe03xDQ H19vqtqD5ao1HlHYNG+lPOxEFNARK++OH1RnhJLfKjr/1ABjD/W42om5S0A68dR8HWwP HeAVZReEzEjxkHmhLa+QTnM62M1z3UhpJCNweLXXuT/C3CU0D4FlYjvkhkEjm4Hq6ZLN mj8Q== X-Gm-Message-State: AOJu0Yxjs97yQGfmLiUT8YcczWYJ09kwhx6aVlQIqluLBeP3ZR9JEWu+ Wm993Mm/+8uVSlsTjBek7lxSCxpk3FGF5IXJ X-Google-Smtp-Source: AGHT+IHXel3rGQ+Xzm5xFbzN7GycW+T/jRwF2RWX8s9nRV5XCnxpKnyFKQREp1gWew8lzaVswTJu0Q== X-Received: by 2002:a05:6a20:244a:b0:19a:2dd3:75df with SMTP id t10-20020a056a20244a00b0019a2dd375dfmr171886pzc.8.1704877270566; Wed, 10 Jan 2024 01:01:10 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 54/65] target/riscv: add rva22s64 cpu Date: Wed, 10 Jan 2024 18:57:22 +1000 Message-ID: <20240110085733.1607526-55-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=alistair23@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877381719100009 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Add a new profile CPU 'rva22s64' to work as an alias of -cpu rv64i,rva22s64 Like the existing rva22u64 CPU already does with the RVA22U64 profile. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-27-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 12fe78fc52..9219c2fcc3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -36,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") +#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a8f4081922..b32681f7f3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1623,6 +1623,13 @@ static void rva22u64_profile_cpu_init(Object *obj) =20 RVA22U64.enabled =3D true; } + +static void rva22s64_profile_cpu_init(Object *obj) +{ + rv64i_bare_cpu_init(obj); + + RVA22S64.enabled =3D true; +} #endif =20 static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -1938,6 +1945,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), #endif }; =20 --=20 2.43.0