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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.01.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 01:00:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877233; x=1705482033; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9+8tnLHFQNGDezXJHjDuhE9l+8HHfjlZ0t10rhaGJNM=; b=PiMw8Zmb4loGIUTa5FrCdJ4d+7qsGH4J7tjbTopBQ3zBzqY9p2E9cvDYl4dyHgwCzK TVL3SHsPIIj9yD/ml5JC6wLWK3qQzz0BFlZ7Zo5oH2j6h7svASUUeTnfxGAjm8AOdNV7 t7Sb8ftx+x9S8mlCYMs5PSvNkdvutg7BqiciL3xRyYLN9s1lD6FnLX11GFOc6f/QQmtk 8qfH5j/u8ifxxz/gue+MwlnyEsGAPdj643/Z0WGT7TySUqVLwqEBXIJz7i6+48rTQU5p I1b6DxV6WTuFgf5Ir6BmKjxFSYsC+Mu1dCIt1dBr5PJqDWsne7QKbL5TVFn0lcD8RJOe P0tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877233; x=1705482033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9+8tnLHFQNGDezXJHjDuhE9l+8HHfjlZ0t10rhaGJNM=; b=rf/h+5suVozCwsHmf6ryrusuN/1GYx4EMlwGf4UcuDg0E1lUSfrheRtaxfl31EhZpa iL52ZOPMnmvRsB2plY0MhS/eTXeMrZrdhHE0cJdE1/CatSVx+vzaWyG+CUtIiPsJiaI4 nBNYOGRvxQ9uJa1Ed2aMLi9h/TSJ8cbml6cTdgnrjn2aODbUedAJgMFQl4DhlOhiqd/z jyp3v8YlqkHHDflUitIUrQd/j2XeIEuNWNJXKhHHcMUz0OXc9FEe1wYmebN0NJItOFm1 un+7qRTaiI5QYHwj2W4tkhMEBhulbVEc7gLYtgv6GSQvZBwXoAy+r2VawUYq6GnZtJMo WaLA== X-Gm-Message-State: AOJu0YzLCvNV8AvbA+XxP2Z8fdNaCHJQoj/IEs3sDbXpSajUSdni+76S qSGhvoQXbCYRWqsQ7G+eKMxHWX1pIUKf+WX5 X-Google-Smtp-Source: AGHT+IET4qGn2tVi7/AMi+bmAHnph5sK4YH0dv2TQHvNEKvA79IQ2ukpf1AEGSvOMs1tGeEVHT6D0A== X-Received: by 2002:a05:6a00:39a2:b0:6da:c208:7044 with SMTP id fi34-20020a056a0039a200b006dac2087044mr621854pfb.40.1704877233332; Wed, 10 Jan 2024 01:00:33 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 44/65] target/riscv/tcg: validate profiles during finalize Date: Wed, 10 Jan 2024 18:57:12 +1000 Message-ID: <20240110085733.1607526-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877982596100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are disabled in the command line. We're also going to disable the profile flag in this case since the profile must include all the mandatory extensions. This flag can be exposed by QMP to indicate the actual profile state after the CPU is realized. After this patch, this will throw warnings: -cpu rv64,rva22u64=3Dtrue,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zihintpause qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicbom qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension = zicboz Note that the following will NOT throw warnings because the profile is being enabled last, hence all its mandatory extensions will be enabled: -cpu rv64,zihintpause=3Dfalse,zicbom=3Dfalse,zicboz=3Dfalse,rva22u64=3Dtrue Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-17-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d2a42a347b..6c9e2e9a28 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -147,6 +147,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static const char *cpu_cfg_ext_get_name(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata->name !=3D NULL; edata++) { + if (edata->ext_enable_offset =3D=3D ext_offset) { + return edata->name; + } + } + + for (feat =3D riscv_cpu_named_features; feat->name !=3D NULL; feat++) { + if (feat->offset =3D=3D ext_offset) { + return feat->name; + } + } + + g_assert_not_reached(); +} + static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) { const RISCVCPUMultiExtConfig *feat; @@ -732,6 +752,54 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 +static void riscv_cpu_validate_profile(RISCVCPU *cpu, + RISCVCPUProfile *profile) +{ + const char *warn_msg =3D "Profile %s mandates disabled extension %s"; + bool send_warn =3D profile->user_set && profile->enabled; + bool profile_impl =3D true; + int i; + + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (!riscv_has_ext(&cpu->env, bit)) { + profile_impl =3D false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + riscv_get_misa_ext_name(bit)); + } + } + } + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + int ext_offset =3D profile->ext_offsets[i]; + + if (!isa_ext_is_enabled(cpu, ext_offset)) { + profile_impl =3D false; + + if (send_warn) { + warn_report(warn_msg, profile->name, + cpu_cfg_ext_get_name(ext_offset)); + } + } + } + + profile->enabled =3D profile_impl; +} + +static void riscv_cpu_validate_profiles(RISCVCPU *cpu) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + riscv_cpu_validate_profile(cpu, riscv_profiles[i]); + } +} + void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -750,6 +818,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) } =20 riscv_cpu_update_named_features(cpu); + riscv_cpu_validate_profiles(cpu); =20 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* --=20 2.43.0