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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.01.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 01:00:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877209; x=1705482009; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qMHclOSf6qVt4kU3bDRKPZmEtxqORxYsuLvB7CuuViM=; b=AiC+aMMR6NgklOrEB1dmvstCP6DREICFCDotg1dd3TWvrsme8njWGykbXHCNwA/kl5 954Pjfa+hWGyGbzH8M4AVhwFvcrigpRWdGHSvxjvyuV862GVuYNJZPlNuumV0dKmfNKN imlPzi1rsxaZyR7Ex3dPBTEpSXsPy7opIUmlqwzjeBCnTCwY4ESyqgG4MYuMllcR3gJf 7MZDefZKw23BGLs03D6gej1E8CQxT8owIoStA/4zFmuXjkgOf+mI3bs0VXJOIKwo5V7f 1++NBpMCrbCeyfcHf3uSTssIo5dGBxBqIo8xNrbb3bdbTICqyUaosp1Z0r10zHj6VlR/ tAZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877209; x=1705482009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qMHclOSf6qVt4kU3bDRKPZmEtxqORxYsuLvB7CuuViM=; b=c0UtE+1U7aK0zpYlCvevfqd3JZtBBfacGnSgyF6pD7wd37V3lYQ5jsD8wuyg6I/gVh bUtdFMP3mHy3jRwzq2fvCcaDOov+u8DRqTvwGwrTr79pxxoUxsWbx2TFdE8xaldDkeqb 2Kgj0iYty/1ur/Ezr/xKNlv6fv4vByUB28KEpO1XqzisLCZecS3w3ieKfptMGnPREPpa 8mFfcPi3BC0IMuSCVogE0b8mH+h9URaY/ExQ/MyEKAQwqqNW7rDETRtDry8HvsDCXELx hPZbnDwHNcA+xI6L1M3j0v5yOBYbGi02a5vCecvSKpNeQh1+xlwCn/A+e4ilxdErlr95 jXAQ== X-Gm-Message-State: AOJu0Yw49SxQGB3mn6zcm3x4C/++TJZ7oYTfJIvv1LMg4nthNqRYeoY0 g9GA6qAdOndc53+euDnEtkLlPdwBG43n1IRD X-Google-Smtp-Source: AGHT+IGexGvJUSwmhcmNHy7WPwMuykeMJ7LnA/JWPf8W42WwGi3dOr5f7fnuUIhh46bC0qxk/nnHbA== X-Received: by 2002:a05:6358:98a7:b0:175:745e:dbef with SMTP id q39-20020a05635898a700b00175745edbefmr729876rwa.61.1704877209210; Wed, 10 Jan 2024 01:00:09 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 38/65] target/riscv/tcg: add user flag for profile support Date: Wed, 10 Jan 2024 18:57:06 +1000 Message-ID: <20240110085733.1607526-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=alistair23@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877998539100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG we'll need some ground work first: - all profiles declared in riscv_profiles[] will be exposed to users. TCG is the main accelerator we're considering when adding profile support in QEMU, so for now it's safe to assume that all profiles in riscv_profiles[] will be relevant to TCG; - we'll not support user profile settings for vendor CPUs. The flags will still be exposed but users won't be able to change them; - profile support, albeit available for all non-vendor CPUs, will be based on top of the new 'rv64i' CPU. Setting a profile to 'true' means enable all mandatory extensions of this profile, setting it to 'false' will disable all mandatory profile extensions of the CPU, which will obliterate preset defaults. This is not a problem for a bare CPU like rv64i but it can allow for silly scenarios when using other CPUs. E.g. an user can do "-cpu rv64,rva22u64=3Dfalse" and have a bunch of default rv64 extensions disabled. The recommended way of using profiles is the rv64i CPU, but users are free to experiment. For now we'll handle multi-letter extensions only. MISA extensions need additional steps that we'll take care later. At this point we can boot a Linux buildroot using rva22u64 using the following options: -cpu rv64i,rva22u64=3Dtrue,sv39=3Dtrue,g=3Dtrue,c=3Dtrue,s=3Dtrue Note that being an usermode/application profile we still need to explicitly set 's=3Dtrue' to enable Supervisor mode to boot Linux. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f12e0620e5..9234254772 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -127,6 +127,19 @@ static bool cpu_cfg_offset_is_named_feat(uint32_t ext_= offset) return false; } =20 +static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offse= t) +{ + switch (feat_offset) { + case CPU_CFG_OFFSET(zic64b): + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + break; + default: + g_assert_not_reached(); + } +} + static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -890,6 +903,71 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) } } =20 +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + int i, ext_offset; + + if (riscv_cpu_is_vendor(obj)) { + error_setg(errp, "Profile %s is not available for vendor CPUs", + profile->name); + return; + } + + if (cpu->env.misa_mxl !=3D MXL_RV64) { + error_setg(errp, "Profile %s only available for 64 bit CPUs", + profile->name); + return; + } + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + profile->user_set =3D true; + profile->enabled =3D value; + + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { + ext_offset =3D profile->ext_offsets[i]; + + if (profile->enabled) { + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + riscv_cpu_enable_named_feat(cpu, ext_offset); + } + + cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); + } + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset), + (gpointer)profile->enabled); + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile =3D opaque; + bool value =3D profile->enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profiles(Object *cpu_obj) +{ + for (int i =3D 0; riscv_profiles[i] !=3D NULL; i++) { + const RISCVCPUProfile *profile =3D riscv_profiles[i]; + + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); + } +} + static bool cpu_ext_is_deprecated(const char *ext_name) { return isupper(ext_name[0]); @@ -1017,6 +1095,8 @@ static void riscv_cpu_add_user_properties(Object *obj) =20 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); =20 + riscv_cpu_add_profiles(obj); + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { qdev_property_add_static(DEVICE(obj), prop); } --=20 2.43.0