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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.59.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 01:00:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877202; x=1705482002; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sO1Eg2zz/Dne3rBFmWD50NqVFWKX6dut/6e4UWZf5FQ=; b=Oz/HnONTOQMTkpt+51WBnN1tyifxhWtwRavzkh8vGCBgpJddO689tBIbo3zu1IV3WI +k+/z2tAb+WOfgeor/Ese9ZvUK7qhWV2AgnX+7btOm9yaEbUdm6+BtD/5GDx742GzcIG QwQ1kTNdkJuurAMQfCqnBHmaRkj8HC1c2AWC08krzEeYfHyXLruMzHGnpOyZm0qoE5D2 v3nGpajH4Em6iCKLZjX5S+9Tl9Aob+DKYJSY1cJ9UzLMvwrnowdHjKZU7AhaMkqFRfSW j3uI6Kzi6Uon2DF3r+rUyG4PUKtC+kSCJMolgvVVAr8rVeNMArUtuwcPK4BO07IQEdg8 Uk1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877202; x=1705482002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sO1Eg2zz/Dne3rBFmWD50NqVFWKX6dut/6e4UWZf5FQ=; b=ZRbnq3RXOHef+/rzpxjoe3dSdNRl45O3Q6RcL2viTXyhDkkm069A48ei3qhfNWy83d UrL6m20J2xrbCtc8suRLnVWnIZg4i6GfcnEKucrcl91OCx/UYiiXp4seVWoqQynezgOl 9M/cXfVclfIqaQl51sxrAx7HBVEBRgJsqMjbwEkWdIFX+oE1oTV4JY1QF41eGoZU3ISK L2ITEeqC09jf+Yzkvajwj0pWoUXRPvTiwvQC8VoxK1mdzO3eAvCbjJkyu3rUYbeS9cv/ zOYPH9TO//W97LHHqxHKEnyCHTfySvoSf8nacCi6eyzkP7ja5HLOVIhyYrIEfHqnlx5S vNdA== X-Gm-Message-State: AOJu0YwRVMBvdglo8YPGgI1Tp2pddp7TC1DNnprlrLnsG/lF7teCnraG s/3F/qo6Gy0CvdV5+WCnEC3cH7fO20lNNkpR X-Google-Smtp-Source: AGHT+IGWOjXTZhsZBDwVukZz4JD6me5iAFXJYR3ZJ5NeWbGftFxLOCPQBEZHlu0M4wMQ9Ssz/tQYhA== X-Received: by 2002:a05:6808:ecf:b0:3bc:5735:23e with SMTP id q15-20020a0568080ecf00b003bc5735023emr714463oiv.23.1704877201914; Wed, 10 Jan 2024 01:00:01 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Andrew Jones Subject: [PULL 36/65] target/riscv: add rva22u64 profile definition Date: Wed, 10 Jan 2024 18:57:04 +1000 Message-ID: <20240110085733.1607526-37-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=alistair23@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877837693100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profi= les Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of features for the CPU, giving users more predicability when running/testing their workloads. QEMU implements all possible extensions of this profile. All the so called 'synthetic extensions' described in the profile that are cache related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa, Zicclsm) since we do not implement a cache model. An abstraction called RISCVCPUProfile is created to store the profile. 'ext_offsets' contains mandatory extensions that QEMU supports. Same thing with the 'misa_ext' mask. Optional extensions must be enabled manually in the command line if desired. The design here is to use the common target/riscv/cpu.c file to store the profile declaration and export it to the accelerator files. Each accelerator is then responsible to expose it (or not) to users and how to enable the extensions. Next patches will implement the profile for TCG and KVM. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20231218125334.37184-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 12 ++++++++++++ target/riscv/cpu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bfa42a0393..5af1666dc0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -76,6 +76,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit); =20 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) =20 +typedef struct riscv_cpu_profile { + const char *name; + uint32_t misa_ext; + bool enabled; + bool user_set; + const int32_t ext_offsets[]; +} RISCVCPUProfile; + +#define RISCV_PROFILE_EXT_LIST_END -1 + +extern RISCVCPUProfile *riscv_profiles[]; + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 29fdd64298..199b581380 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1523,6 +1523,38 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +/* + * RVA22U64 defines some 'named features' or 'synthetic extensions' + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa + * and Zicclsm. We do not implement caching in QEMU so we'll consider + * all these named features as always enabled. + * + * There's no riscv,isa update for them (nor for zic64b, despite it + * having a cfg offset) at this moment. + */ +static RISCVCPUProfile RVA22U64 =3D { + .name =3D "rva22u64", + .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .ext_offsets =3D { + CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), + CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), + CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), + CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), + + /* mandatory named features for this profile */ + CPU_CFG_OFFSET(zic64b), + + RISCV_PROFILE_EXT_LIST_END + } +}; + +RISCVCPUProfile *riscv_profiles[] =3D { + &RVA22U64, + NULL, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 --=20 2.43.0