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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 00:59:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877194; x=1705481994; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JJ1Ad2Yx9zcxdVbi06S6IYr1t/IrV0YCKQv0v0IDTZI=; b=iB5A9DzyxZq0mtWJy9vnuWKcbMjFw1ejGZScTAWTt8YEF8Kag4IADhs14rXFDSztk3 eUSAfXfijolfqMG8jvGsnW4cisPglTpjekm8usYDvt6QlxM3yEHV9Bz4KWSYCC8m1aFt DeHY9jZXgSLOodlE1Xw5KMfA8fos4yn1S0KRjInVLguNCrv8bsfurL4i7dbE6xsLAi4q qTRVCcKih7oNk50W3l21ZHPt398PLUov+GHlLVWam9jEpvHgDyxc2uT51HCfMxzvAOcx 4/3dqHB5wvhOTBEj8LqVgtl7cuJJTr8CLPkIjnfgfae+npc1mE44WuJt0nsty76J7LJ6 uQVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877194; x=1705481994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JJ1Ad2Yx9zcxdVbi06S6IYr1t/IrV0YCKQv0v0IDTZI=; b=uyJ4tnF257bgbPPkw1iitn2QbuJa+QF+C4+wJfTzZPNdQTjD+Am7kwge4CX+Hi/k08 fBMTawbBqK+k+DWMvVBm9tklW1cloFSJdykNvPyrBDv3WXI5mQovEl4el1mOfuKABxdR bx+ISAI7tLNICb0j0WGBZwYii4D9BcbMCBZxqTe0yTrKSxnGnAvAy3fB1uWVlb4t/mVK g+yGJoSg8LdBoH/2zEtzLJUtCYNAjZIpsbrauclvMfTJByScHHfPX+WXgPmP24eGR5S8 nNfAkAdlfqY5gVpGjbNp8sggujADizoc2eeKmtbaQRu7CjJme6vB6N1vhYuXhi3GcizQ ydaQ== X-Gm-Message-State: AOJu0YxgvdJHJ0dDYxndGXu8GOJlG2DFfXhT3eTOUIRAOmr+Cs8mAPG6 JJjY6jJalyN4jy8Wm9qeuv0HOcDAyVjfuS1+ X-Google-Smtp-Source: AGHT+IG7fv1c41U7aIygl89styviuF9wHf/l0DKXqDtqFsEXLYI5/qdbEGfo7MsyU3bzbhLLke/Fbg== X-Received: by 2002:a05:6a20:12c2:b0:19a:1972:f728 with SMTP id v2-20020a056a2012c200b0019a1972f728mr1083088pzg.31.1704877194434; Wed, 10 Jan 2024 00:59:54 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 34/65] target/riscv/tcg: add 'zic64b' support Date: Wed, 10 Jan 2024 18:57:02 +1000 Message-ID: <20240110085733.1607526-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877254898100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications using this profile expects 64 bytes cache blocks. To make the upcoming RVA22U64 implementation complete, we'll zic64b as a 'named feature', not a regular extension. This means that: - it won't be exposed to users; - it won't be written in riscv,isa. This will be extended to other named extensions in the future, so we're creating some common boilerplate for them as well. zic64b is default to 'true' since we're already using 64 bytes blocks. If any cache block size (cbo{m,p,z}_blocksize) is changed to something different than 64, zic64b is set to 'false'. Our profile implementation will then be able to check the current state of zic64b and take the appropriate action (e.g. throw a warning). [1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles= .pdf Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 6 ++++++ target/riscv/tcg/tcg-cpu.c | 26 ++++++++++++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2725528bb5..bfa42a0393 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -765,6 +765,7 @@ typedef struct RISCVCPUMultiExtConfig { extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; extern Property riscv_cpu_options[]; =20 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2da8ac9582..350ea44e50 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -117,6 +117,7 @@ struct RISCVCPUConfig { bool ext_smepmp; bool rvv_ta_all_1s; bool rvv_ma_all_1s; + bool zic64b; =20 uint32_t mvendorid; uint64_t marchid; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce0a3ded04..29fdd64298 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1443,6 +1443,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_= exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { + MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), + + DEFINE_PROP_END_OF_LIST(), +}; + /* Deprecated entries marked for future removal */ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] =3D { MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e9f980805e..f12e0620e5 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) +{ + const RISCVCPUMultiExtConfig *feat; + + for (feat =3D riscv_cpu_named_features; feat->name !=3D NULL; feat++) { + if (feat->offset =3D=3D ext_offset) { + return true; + } + } + + return false; +} + static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, uint32_t ext_offset) { @@ -123,6 +136,10 @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState = *env, return; } =20 + if (cpu_cfg_offset_is_named_feat(ext_offset)) { + return; + } + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); =20 if (env->priv_ver < ext_priv_ver) { @@ -293,6 +310,13 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_update_named_features(RISCVCPU *cpu) +{ + cpu->cfg.zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && + cpu->cfg.cbop_blocksize =3D=3D 64 && + cpu->cfg.cboz_blocksize =3D=3D 64; +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -662,6 +686,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) return; } =20 + riscv_cpu_update_named_features(cpu); + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available --=20 2.43.0