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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.59.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 00:59:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877191; x=1705481991; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pSoRvl4XGNPKXBSy4UlQSsI1DM3kmfBRZBEFpQkHixs=; b=HJxWX/8wZciXhcTLnyh3eoPRCbC73WDB3oNUtgsVfkToEHIc49SC0JPEQzYno1ZCZj ay1gFqxoLMbMUKrCHVRytMRS9CH5YsI9GPBdywXuz57iROOZyHQCftFSESLMZxJNoTjY nvGmcKBRZoOXxf2vHviqEmObocJedlMrXKMKFFlYW6Np3xUyoxgftA6qIZdz/21jc5J+ rw+gwimngWdONq5cFuefxZ+pWJoQ9T3nZpM/xplU/rsAa8oum4MB7P8R3y5yXI5m1nqJ 8nJsNNFD0laCTnVBU31CCHMIyCWXpfMydD5ogFsMeKBa2CFIg+zn0JdTuvdM7bSMA8ke 9HJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877191; x=1705481991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pSoRvl4XGNPKXBSy4UlQSsI1DM3kmfBRZBEFpQkHixs=; b=anpNdd9PfIzXFNfVYXEgWU/DGl6q2XycDxsAT2HjdW7aB5353br6Ae/LUITXr8sg3r tejjRxIC94LX7Jc198t/hrUES1oAQT6h95hg3rkJ0TVclUHEWqWqhH+tNmHysBAZGzSX WIXUcghRDX8Dyzo/6EvzoBubGQaiYWSBWs8J3Jjd4+gJqygCO9ks1pduV0zvtdI4+QaN yHmIJR5K1ELgGc8zPaRGLow7JvW1CPxT2cy4mjwIaptVqk4HEqRi6xa/Ax4VL8ugqQeh dwiyg2oiArjLuFw/c0srdIehzTHLXR5WzKFJbGdCnd46Z9SdCUImc6edUXDuLNy76o8N Rb5w== X-Gm-Message-State: AOJu0YybDSJMjnxEgBxAhSJND6MvVrZuPVYtI5xij3CF0O43YwT4mugl 0eR5DZxbonGWfG81wDYsYm55Jzx31gvjbxXT X-Google-Smtp-Source: AGHT+IEZ5ZcV6331AdvQrTFUoMS68gtDZuttvSHdy5+1adZHcHtzo2vU4thyyB5c4RQN/Gz0yS43ZA== X-Received: by 2002:a05:6a00:278d:b0:6d9:bbc9:98d9 with SMTP id bd13-20020a056a00278d00b006d9bbc998d9mr766215pfb.8.1704877190694; Wed, 10 Jan 2024 00:59:50 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 33/65] target/riscv: add zicbop extension flag Date: Wed, 10 Jan 2024 18:57:01 +1000 Message-ID: <20240110085733.1607526-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877279085100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which are now no-ops. The RVA22U64 profile mandates zicbop, which means that applications that run with this profile might expect zicbop to be present in the riscv,isa DT and might behave badly if it's absent. Adding zicbop as an extension will make our future RVA22U64 implementation more in line with what userspace expects and, if/when cache block prefetch operations became relevant to QEMU, we already have the extension flag to turn then on/off as needed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 ++ hw/riscv/virt.c | 5 +++++ target/riscv/cpu.c | 3 +++ 3 files changed, 10 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index d516de4a44..2da8ac9582 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -65,6 +65,7 @@ struct RISCVCPUConfig { bool ext_zicntr; bool ext_zicsr; bool ext_zicbom; + bool ext_zicbop; bool ext_zicboz; bool ext_zicond; bool ext_zihintntl; @@ -143,6 +144,7 @@ struct RISCVCPUConfig { uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; + uint16_t cbop_blocksize; uint16_t cboz_blocksize; bool mmu; bool pmp; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4194ddcef1..f9fd1341fc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -250,6 +250,11 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, cpu_ptr->cfg.cboz_blocksize); } =20 + if (cpu_ptr->cfg.ext_zicbop) { + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbop-block-siz= e", + cpu_ptr->cfg.cbop_blocksize); + } + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33d25d12a6..ce0a3ded04 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -78,6 +78,7 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, = RVD, RVV, */ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom), + ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr), @@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), =20 MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true), + MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true), MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true), =20 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), @@ -1509,6 +1511,7 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), + DEFINE_PROP_UINT16("cbop_blocksize", RISCVCPU, cfg.cbop_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), --=20 2.43.0