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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 00:59:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877182; x=1705481982; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YseZjKT6UGh5rCpwBXSTurbsrdaCV7Ypvqgj2xOMRpE=; b=GckwaZaqUNDKoSnWvaTuQWERsMla6BmWXseQtnn1aPth2SH1dC7sDnP/JqnuM+Rsxj YxOS5HoKOqQT1cpjOe0sKJlkmXOF6Dkw9sLTm1zR14LSGGEZRhmV52Aa2+4aX8V7BWbD qXfn8rQf/aVwU3zOXpRA0I0nxbsMURTL8GJlKOhobqsHVquHWofg01lN8cXIBGoGSwi/ fhIiRl6N5oiko8cXNxusNqy8Z5n96pbnFoHYjzOnjk0NYK18GNrph6uOFVc/mQaR4ScY BzztuHPlhHSvm0PFYGj0Ds/gZ67W8ozeJnZKyA0VXtfjKFRlHQAbbgmHKGLgicaki4qp SNiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877182; x=1705481982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YseZjKT6UGh5rCpwBXSTurbsrdaCV7Ypvqgj2xOMRpE=; b=vJXm/Oti4j+D5WGgnk/6s4+E5fiDzz7HsLXXrWd6uT1thqoob2+soADPPpGEefP5Bc Ow1oKLMWy0lQ4w9ixavgZW8KlMqHnV2c46JPzdrQnq/l/WnTUl9YD8T7g2D+xUa6vbm0 cUYpHDN33nHhiRu7yfp7OlEhW15yFVP2zIYqp07Q/5LKc0pH4WFtBBkPSeR6fWA/K482 EmTZQhS8WskwgNukD6RAdjnnZHscb8RB6yaw+bJAijzT4MFH7F1xRpsBISM1qTP0srrU +NOPhv25WDhCNjcA95O/uiNpbRkjN4IVxhIqSGFW4YGDkWKg6GPh8yEd3sIqvKcWRpKx 8nJA== X-Gm-Message-State: AOJu0YyRDw/NoNJQZDn+8y49TSbj9+3w4IaoVfyV5EhZWHekSCYAx3P0 eK5Jny/x0Fh6ecsrXhItOARF5eBpJp+WQR5O X-Google-Smtp-Source: AGHT+IG4lN9RageaYucaoWD/2gA1T888L+KJ/GaQMiWCyeYAzpMrAJqoAS9D/yFWhmfCHBJPy6yusQ== X-Received: by 2002:a05:6a00:1d1c:b0:6d9:aad2:46c with SMTP id a28-20020a056a001d1c00b006d9aad2046cmr1187783pfx.7.1704877182396; Wed, 10 Jan 2024 00:59:42 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 31/65] target/riscv/tcg: update priv_ver on user_set extensions Date: Wed, 10 Jan 2024 18:56:59 +1000 Message-ID: <20240110085733.1607526-32-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=alistair23@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877287065100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver =3D 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will then need to manually set priv_ver to something other than 1.10 to enable the extensions they want, which is not ideal. Change the setter() of extensions to allow user enabled extensions to bump the priv_ver of the CPU. This will make it convenient for users to enable extensions for CPUs that doesn't set a default priv_ver. This change does not affect any existing CPU: vendor CPUs does not allow extensions to be enabled, and generic CPUs are already set to priv_ver LATEST. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7174abb7f5..e9f980805e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_of= fset) g_assert_not_reached(); } =20 +static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset) +{ + int ext_priv_ver; + + if (env->priv_ver =3D=3D PRIV_VERSION_LATEST) { + return; + } + + ext_priv_ver =3D cpu_cfg_ext_get_min_version(ext_offset); + + if (env->priv_ver < ext_priv_ver) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D ext_priv_ver; + } +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -762,6 +782,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + if (misa_bit =3D=3D RVH && env->priv_ver < PRIV_VERSION_1_12_0) { + /* + * Note: the 'priv_spec' command line option, if present, + * will take precedence over this priv_ver bump. + */ + env->priv_ver =3D PRIV_VERSION_1_12_0; + } + env->misa_ext |=3D misa_bit; env->misa_ext_mask |=3D misa_bit; } else { @@ -891,6 +919,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor= *v, const char *name, return; } =20 + if (value) { + cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); + } + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); } =20 --=20 2.43.0