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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 00:59:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877178; x=1705481978; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IOdvKz0W/nb7uzqZzY4cXwsk1ivtQ658u5A6kThiDZo=; b=Iriof5b/Rn9GTTCMAYBkhTbJuIoAkaFjtjDOZcyZfhxtui07tWU3y02gU+dhZE8raK RSfHDlaUQ6QGnO7M1nfyFF2Yqlg+8qSqbnxQc0ipNLt+K7lvFqSl3p9JFiFmQvvAe20E +aznsD5DneYXob9lvmIXDBvDuLSTkcXsyMlfiSZUympTc00O+xZPkjgtwSwgYb0qw7u5 vHKf8R+PxvDuYLjLndl+pyddtVJBeFjsxLiC6llSF5aasaESWgx5TGyzoVUq9lYvnrl+ AaAX6huJ1M3z3VP3lojVtnlB4yXpgVIQ9f72vPpSgKwnY4JzzXD6VtmR3LGbyAU778Kk f/gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877178; x=1705481978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IOdvKz0W/nb7uzqZzY4cXwsk1ivtQ658u5A6kThiDZo=; b=G1zs8fz+xLtel422dmkdZRvZJmQMkr2AEE3fsssIRV2l8alCZ7Do37VbXbwEPkFupP w0FI4wPiJZJ9h8gIApNsU5yLXpmHRxDRfyPDT2deF5qULEQA05Bf0p6N3T2utm6SRr8P pIGqPT1f6YBKJczPYMZS0zmNQ/rI75IVRf9bD3vN2iKFdFWqBytRmrlApKCfmNKAnQCd qOd86MpEZMJejJjOtVtytxVLTYPa2RVFXXBUmmjECPJYf8l4nNKGvC/5OVSNDVRzr0QK fhYbsv12MXAcjT5qFcX02ApIx6IlJZBJEKWPJnL4LEc7uUcFi98lLEuLzw8hnC+Ei9Ha k+2A== X-Gm-Message-State: AOJu0YyvN8GDj3QvJkPzIGy5IV8rLuHrKMZPXQEyDdT6Xrk6THGGBkNk pptPrE7Lj6BvLhf0/rHqnkuVmPle375AgyOz X-Google-Smtp-Source: AGHT+IHXhg67XGP2+HK1SNaNtlpuFItG6EJ+Lj1pNXodGvul55iVV9pmrDBS3RaBpYrM5ZYhs7/wTw== X-Received: by 2002:a05:6808:3a1b:b0:3bb:c699:b1b1 with SMTP id gr27-20020a0568083a1b00b003bbc699b1b1mr853605oib.55.1704877178696; Wed, 10 Jan 2024 00:59:38 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 30/65] target/riscv/tcg: do not use "!generic" CPU checks Date: Wed, 10 Jan 2024 18:56:58 +1000 Message-ID: <20240110085733.1607526-31-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877903907100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu inste= ad of "not generic". The "generic CPU" checks remaining are from riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before applying default values for the extensions. This leaves us with: - vendor CPUs will not allow extension enablement, all other CPUs will; - generic CPUs will inherit default values for extensions, all others won't. And now we can add a new, third CPU type, that will allow extensions to be enabled and will not inherit defaults, without changing the existing logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 29b5a88931..7174abb7f5 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -668,6 +668,11 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 +static bool riscv_cpu_is_vendor(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) !=3D NULL; +} + /* * We'll get here via the following path: * @@ -736,7 +741,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, target_ulong misa_bit =3D misa_ext_cfg->misa_bit; RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -750,7 +755,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *= v, const char *name, } =20 if (value) { - if (!generic_cpu) { + if (vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); @@ -855,7 +860,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, { const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; RISCVCPU *cpu =3D RISCV_CPU(obj); - bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool vendor_cpu =3D riscv_cpu_is_vendor(obj); bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { @@ -879,7 +884,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 - if (value && !generic_cpu) { + if (value && vendor_cpu) { g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU does not allow enabling extensions", cpuname); --=20 2.43.0