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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 00:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877175; x=1705481975; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bMChAFX8p3aMIvWR43AzoqrqUp6gB64xGTP36+CYcjE=; b=ZAL7GcHN65CNPxt/PzIfTyp2bXH43UAndZm4RWkUv8RwTbpl/+S8UfJjhj4/hpQSuw 2mTqiDPy3vD2w1JweJuHa1HwBrfIRmq8dDab7znQHA22wWs0wBFcdZBcZVDanzuuKQEZ jtyV8fxRLFEN25vcwMMhhO1kEfIAMjuJVzRfQa6CgSNq9lFsjWdTpDwnfv6QsdBfTCZM aj0k/n2HLxswwVYQharKlZ1Od8STgRZfvR1RRkf9KU7vUqSGocuWmqWBEpKMjfkhf+Bz kXK7fNZW7etHvTzoA9EcArVYNCN+/jU5Q4IIqr/ZquYiaHoUKp/Rrvwv7sWGHUwdn9a3 BmdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877175; x=1705481975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bMChAFX8p3aMIvWR43AzoqrqUp6gB64xGTP36+CYcjE=; b=uYFTwzrYjgufE5r280Epzti4J4zjb1xYsHql2A4DA77X1GneGOW/FISRxpNQrYZOSq 0q21jeRzqyidkHww+fsyHiz+aUb6XftbiOxTEuVc0K57ffgtvmkBc6kBgkMA3JfSnBHg NWW4gufe1SseqjM6/msdYl4Oc5drL9YpFr4H6cwqxl99eIWKAmp2t6wceJos/LWk5qYZ rlC08v5fkgxzoRWp77C9P4FGL5BqWpr03DOVm+92aCyVRIsvVSUYZtzrDvWhsjViDCcd 4C+p4kD+BC+k2kNpFJ3v01GduWSr3etYkGf4kBdoZDcq0r8ML4Zl/pGa8avudkayCFi7 6n+Q== X-Gm-Message-State: AOJu0Yy574zg9+jb1lVEIWHuL8jEvm6/42V8Nnojmx33A4fCENgRT+M/ Jkjappxe89OEiwtzHdQtjCglQ/rZDkXDfXN8 X-Google-Smtp-Source: AGHT+IFMGrEsG0091lWl9J1H8igK78KqzIg5sWOncAtI7R71vlTF+H45psi1U9hbJs2MXOLbP7z97w== X-Received: by 2002:a05:6808:ecd:b0:3bc:1517:ecb9 with SMTP id q13-20020a0568080ecd00b003bc1517ecb9mr710801oiv.56.1704877175576; Wed, 10 Jan 2024 00:59:35 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 29/65] target/riscv: create TYPE_RISCV_VENDOR_CPU Date: Wed, 10 Jan 2024 18:56:57 +1000 Message-ID: <20240110085733.1607526-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=alistair23@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877264970100009 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the existing vendor CPUs and change the existing logic to not imply that "not generic" means vendor CPUs. Let's add the "vendor" CPU type first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20231218125334.37184-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 91b3361dec..ca7dd509e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -23,6 +23,7 @@ =20 #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" +#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 21b0eddf6f..bf0235305e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1748,6 +1748,13 @@ char *riscv_isa_string(RISCVCPU *cpu) .instance_init =3D initfn \ } =20 +#define DEFINE_VENDOR_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_VENDOR_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1765,21 +1772,26 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, + { + .name =3D TYPE_RISCV_VENDOR_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; --=20 2.43.0