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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id t65-20020a628144000000b006d9879ba6besm3223814pfd.170.2024.01.10.00.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 00:58:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704877096; x=1705481896; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+yMicriNP9FRxv1gu/4gdBxKprzQt1ebDJy/63beWZc=; b=MyRYMJjLpkEynsFj7Sa87OZgKhY0kMX1Qp/uB5hFoyTOFRv2WVW3qSNrrtsyuC5tBz V3twqfSeloZKmcxsX5pb9mKobl6GP0pJorlgSRSgLwpBPj0B7QFR4zb99NiOibO95Y5A QCyDWKvWiE/f35gdorKxlMYer4CZZjr2hV+XN/CxoeUiQGuAm0UhSA3Egf39scCqk2xf yABg67xNjlZVQmq6Ip8NvBg2x1czxPpViQho2hknntNMgdDYBVdZKWdXlwR0JAsHs3z4 19jC0PY4gMhYZ9dREbJunD2RzqwsGrCGj1xvnSUvOMOZ4E2HftEk62f1eMFhv9LK3mXo wLHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704877096; x=1705481896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+yMicriNP9FRxv1gu/4gdBxKprzQt1ebDJy/63beWZc=; b=LIcM2ynqVMvimknEwedSlGQWxraXSxFFk/bQu+B494FKsXkHGYuhaQMXOXY4+TcAFN 5C8iZWwSrNWyBIF5+MsNQz87lhzIRrxWnTFa3zqwDM0ZbXJM+wM9BfKpKP1j7RvlHK/E da+ED9TdnK326VcKK1PITgOP8vtzL5HkBFA/sRxE79Zk5+XoF3Cb/HSMAlyU50IOrbSu NHCoO2J9ObZKMWBqsSOvb7lvU48HlMdgiGBMdAzy8pV/66jw2mPvU1JDdrATo6MgbugM 0cfpkUjaCkO9P/fnHrSRtnfZHxNCzv2N63CQii0v5rYOs5WDZ5CyIcRKNOf9l4y8p8P+ psPA== X-Gm-Message-State: AOJu0Yy8rYa9QaPM/t+lfyN4dSA8CYZPOctxqBOp0Sj2EZiffk8itZm/ dbd7MYZrhIIYSuDD3M5cnmYgmiPKT0mOc40j X-Google-Smtp-Source: AGHT+IH4yl0D5EtW6Y5ogt8P/0TXti7/sFTsly4JxPnI11xRYmtgOrCzKHdVP+kbgyMfO1KCRgy+IA== X-Received: by 2002:a05:6a00:d66:b0:6d9:b320:94c9 with SMTP id n38-20020a056a000d6600b006d9b32094c9mr737704pfv.33.1704877095415; Wed, 10 Jan 2024 00:58:15 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 09/65] target/riscv/kvm: change timer regs size to u64 Date: Wed, 10 Jan 2024 18:56:37 +1000 Message-ID: <20240110085733.1607526-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240110085733.1607526-1-alistair.francis@wdc.com> References: <20240110085733.1607526-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704877118163100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at this moment we'll return u32 regs if we're running a RISCV32 target. Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20231208183835.2411523-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 9370c72f9b..b7871b2f8f 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -88,7 +88,7 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint6= 4_t idx) #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR,= \ KVM_REG_RISCV_CSR_REG(name)) =20 -#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TI= MER, \ +#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ KVM_REG_RISCV_TIMER_REG(name)) =20 #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) @@ -111,17 +111,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, u= int64_t idx) } \ } while (0) =20 -#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ +#define KVM_RISCV_GET_TIMER(cs, name, reg) \ do { \ - int ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®);= \ + int ret =3D kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ if (ret) { \ abort(); \ } \ } while (0) =20 -#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ +#define KVM_RISCV_SET_TIMER(cs, name, reg) \ do { \ - int ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®);= \ + int ret =3D kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ if (ret) { \ abort(); \ } \ @@ -649,10 +649,10 @@ static void kvm_riscv_get_regs_timer(CPUState *cs) return; } =20 - KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); - KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); - KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); - KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); + KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); + KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); + KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); + KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); =20 env->kvm_timer_dirty =3D true; } @@ -666,8 +666,8 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) return; } =20 - KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); - KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); + KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); + KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); =20 /* * To set register of RISCV_TIMER_REG(state) will occur a error from K= VM @@ -676,7 +676,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) * TODO If KVM changes, adapt here. */ if (env->kvm_timer_state) { - KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); + KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); } =20 /* @@ -685,7 +685,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) * during the migration. */ if (migration_is_running(migrate_get_current()->state)) { - KVM_RISCV_GET_TIMER(cs, env, frequency, reg); + KVM_RISCV_GET_TIMER(cs, frequency, reg); if (reg !=3D env->kvm_timer_frequency) { error_report("Dst Hosts timer frequency !=3D Src Hosts"); } --=20 2.43.0