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Tue, 09 Jan 2024 20:02:13 -0800 (PST) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] target/riscv: Raise an exception when sdtrig is turned off Date: Wed, 10 Jan 2024 09:32:03 +0530 Message-Id: <20240110040203.1920924-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110040203.1920924-1-hchauhan@ventanamicro.com> References: <20240110040203.1920924-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=hchauhan@ventanamicro.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704859396222100001 Content-Type: text/plain; charset="utf-8" When sdtrig is turned off by "sdtrig=3Dfalse" option, raise and illegal instruction exception on any read/write to sdtrig CSRs. Signed-off-by: Himanshu Chauhan --- target/riscv/csr.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c50a33397c..b9ca016ef2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3854,6 +3854,10 @@ static RISCVException write_pmpaddr(CPURISCVState *e= nv, int csrno, static RISCVException read_tselect(CPURISCVState *env, int csrno, target_ulong *val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + *val =3D tselect_csr_read(env); return RISCV_EXCP_NONE; } @@ -3861,6 +3865,10 @@ static RISCVException read_tselect(CPURISCVState *en= v, int csrno, static RISCVException write_tselect(CPURISCVState *env, int csrno, target_ulong val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + tselect_csr_write(env, val); return RISCV_EXCP_NONE; } @@ -3868,6 +3876,10 @@ static RISCVException write_tselect(CPURISCVState *e= nv, int csrno, static RISCVException read_tdata(CPURISCVState *env, int csrno, target_ulong *val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* return 0 in tdata1 to end the trigger enumeration */ if (env->trigger_cur >=3D RV_MAX_TRIGGERS && csrno =3D=3D CSR_TDATA1) { *val =3D 0; @@ -3885,6 +3897,10 @@ static RISCVException read_tdata(CPURISCVState *env,= int csrno, static RISCVException write_tdata(CPURISCVState *env, int csrno, target_ulong val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + if (!tdata_available(env, csrno - CSR_TDATA1)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -3896,6 +3912,10 @@ static RISCVException write_tdata(CPURISCVState *env= , int csrno, static RISCVException read_tinfo(CPURISCVState *env, int csrno, target_ulong *val) { + if (!riscv_cpu_cfg(env)->ext_sdtrig) { + return RISCV_EXCP_ILLEGAL_INST; + } + *val =3D tinfo_csr_read(env); return RISCV_EXCP_NONE; } --=20 2.34.1