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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=shlomopongratz@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704804397941100002 Content-Type: text/plain; charset="utf-8" Hanlde wrap around caused by the fact that perior to version 460A the limit was 32bit quantity. See Linux kernel code in: drivers/pci/controllers/dwc/pcie-designware.c function: __dw_pcie_prog_outbound_atu Now in a 64bit system the range can be above 4G but as long as the limit itself is less then 4G the overflow is avoided Signed-off-by: Shlomo Pongratz ---- Changes since v1: * Seperate subject and description --- hw/pci-host/designware.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index dd9e389c07..7ce4a6b64d 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -269,11 +269,24 @@ static void designware_pcie_update_viewport(Designwar= ePCIERoot *root, { const uint64_t target =3D viewport->target; const uint64_t base =3D viewport->base; - const uint64_t size =3D (uint64_t)viewport->limit - base + 1; const bool enabled =3D viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; + uint64_t tbase, tlimit, size; =20 MemoryRegion *current, *other; =20 + /* + * Hanlde wrap around caused by the fact that perior to version 460A + * the limit was 32bit quantity. + * See Linux kernel code in: + * drivers/pci/controllers/dwc/pcie-designware.c + * function: __dw_pcie_prog_outbound_atu + * Now in a 64bit system the range can be above 4G but as long as + * the limit itself is less then 4G the overflow is avoided + */ + tbase =3D base & 0xffffffff; + tlimit =3D 0x100000000 + (uint64_t)viewport->limit; + size =3D ((tlimit - tbase) & 0xffffffff) + 1; + if (viewport->cr[0] =3D=3D DESIGNWARE_PCIE_ATU_TYPE_MEM) { current =3D &viewport->mem; other =3D &viewport->cfg; --=20 2.25.1