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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=n.ostrenkov@gmail.com; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704722660559100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nikita Ostrenkov --- hw/arm/Kconfig | 2 ++ hw/arm/fsl-imx6.c | 25 ++++++++++++++++++++++ include/hw/arm/fsl-imx6.h | 44 ++++++++++++++++++++------------------- 3 files changed, 50 insertions(+), 21 deletions(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 660f49db49..2559d1317b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -530,6 +530,7 @@ config FSL_IMX31 =20 config FSL_IMX6 bool + imply PCIE_DEVICES imply I2C_DEVICES select A9MPCORE select IMX @@ -537,6 +538,7 @@ config FSL_IMX6 select IMX_I2C select IMX_USBPHY select WDT_IMX2 + select PCI_EXPRESS_DESIGNWARE select SDHCI =20 config ASPEED_SOC diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index b2153022c0..27702b6d6d 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -22,6 +22,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" +#include "hw/misc/unimp.h" #include "hw/usb/imx-usb-phy.h" #include "hw/boards.h" #include "hw/qdev-properties.h" @@ -102,6 +103,8 @@ static void fsl_imx6_init(Object *obj) =20 =20 object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); + + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); } =20 static void fsl_imx6_realize(DeviceState *dev, Error **errp) @@ -109,6 +112,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) MachineState *ms =3D MACHINE(qdev_get_machine()); FslIMX6State *s =3D FSL_IMX6(dev); uint16_t i; + qemu_irq irq; unsigned int smp_cpus =3D ms->smp.cpus; =20 if (smp_cpus > FSL_IMX6_NUM_CPUS) { @@ -421,6 +425,27 @@ static void fsl_imx6_realize(DeviceState *dev, Error *= *errp) FSL_IMX6_WDOGn_IRQ[i])); } =20 + /* + * PCIe + */ + sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR); + + irq =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); + + /* + * PCIe PHY + */ + create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR, + FSL_IMX6_PCIe_SIZE); + /* ROM memory */ if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", FSL_IMX6_ROM_SIZE, errp)) { diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 519b871014..61c593ffd2 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -32,6 +32,7 @@ #include "hw/net/imx_fec.h" #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" +#include "hw/pci-host/designware.h" #include "exec/memory.h" #include "cpu.h" #include "qom/object.h" @@ -55,27 +56,28 @@ struct FslIMX6State { DeviceState parent_obj; =20 /*< public >*/ - ARMCPU cpu[FSL_IMX6_NUM_CPUS]; - A9MPPrivState a9mpcore; - IMX6CCMState ccm; - IMX6SRCState src; - IMX7SNVSState snvs; - IMXSerialState uart[FSL_IMX6_NUM_UARTS]; - IMXGPTState gpt; - IMXEPITState epit[FSL_IMX6_NUM_EPITS]; - IMXI2CState i2c[FSL_IMX6_NUM_I2CS]; - IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS]; - SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; - IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; - IMX2WdtState wdt[FSL_IMX6_NUM_WDTS]; - IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS]; - ChipideaState usb[FSL_IMX6_NUM_USBS]; - IMXFECState eth; - MemoryRegion rom; - MemoryRegion caam; - MemoryRegion ocram; - MemoryRegion ocram_alias; - uint32_t phy_num; + ARMCPU cpu[FSL_IMX6_NUM_CPUS]; + A9MPPrivState a9mpcore; + IMX6CCMState ccm; + IMX6SRCState src; + IMX7SNVSState snvs; + IMXSerialState uart[FSL_IMX6_NUM_UARTS]; + IMXGPTState gpt; + IMXEPITState epit[FSL_IMX6_NUM_EPITS]; + IMXI2CState i2c[FSL_IMX6_NUM_I2CS]; + IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS]; + SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; + IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; + IMX2WdtState wdt[FSL_IMX6_NUM_WDTS]; + IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS]; + ChipideaState usb[FSL_IMX6_NUM_USBS]; + IMXFECState eth; + DesignwarePCIEHost pcie; + MemoryRegion rom; + MemoryRegion caam; + MemoryRegion ocram; + MemoryRegion ocram_alias; + uint32_t phy_num; }; =20 =20 --=20 2.34.1