From nobody Tue Nov 26 22:25:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=rfc1149.net ARC-Seal: i=1; a=rsa-sha256; t=1704565003; cv=none; d=zohomail.com; s=zohoarc; b=DOvS4uSsTMkqCoo3zNMQE1Qb2D17s9/q3fe/rEIOJTlQ+GKWVrK4zPVaMZHZKA2MlEgrONpkbE/1UFZsVfetTDq0LA+fIres8kKiK5ODXe2EMoKGgpxtVc77OBTpxconsoqFwyaf35b9ASPv/QgMXw+Ws49yS1gmV2v7DhXS1qM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704565003; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pdCuOTWebVr2BHVGM6RBWWIekbx4EMCOFpe8MOyRVbo=; b=kFCwCPqRg/nB63XoldpAxWCzDuAocf1jwN7wD/ope/8V3m8iEUCi/pA8Uks2RHK0pLpc7aYoxitOAeptVErWU+tjS/YwSTZRWoTCF18bW7lUUujZCdU7J4vRBcfvEnLlQTUXdHIfmnAU/Ad72rLjHOEPnLFQpITykxmWOB9hhrc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704565003505796.2737089307778; Sat, 6 Jan 2024 10:16:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rMBCW-0006Qm-Fy; Sat, 06 Jan 2024 13:15:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rMBCS-0006MU-4S; Sat, 06 Jan 2024 13:15:12 -0500 Received: from zoidberg.rfc1149.net ([195.154.227.159]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rMBCP-0001vy-RT; Sat, 06 Jan 2024 13:15:11 -0500 Received: from 127.0.0.1 (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (Client did not present a certificate) by zoidberg.rfc1149.net (Postfix) with ESMTPSA id 4215080026; Sat, 6 Jan 2024 19:15:04 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rfc1149.net; s=smtp; t=1704564904; bh=kNhppvo/CRU4H84/steItY4yhrW3Ab/UuhFo++kdr+M=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NF0BJAQQOwugLGE5o+IyBIcpSK1ehpS2hnwlLnDAmcXxB79+PacfTCZugGJRcMpby Lx6ze1evzOLT9JB5B57jQrr8uTF+EiibkeJI+QeEC8b4du+mCAyDd6NY+1V3wHaBZq wg5UWKZ2CDjJ1q/z+eVMwGq4aWS1Cn+0Q/+hZcNVBSPVO4AVN0hjnl/lA8WQ16mWGa WhFDc9VmrEZH9fQ4UvfBLMDE5RTsawON8y1aBXhbGMYCmVSP9NA3XPijpLsz3k0By+ KWJDDcsWqsfY70EBOtV629RHX3RHv/pQ2EwZtY3UKiaFXDkCnF02WWGXn6u3OvKD7H GFrYRToMMIuHg== From: Samuel Tardieu To: qemu-devel@nongnu.org Cc: Anton Kochkov , qemu-arm@nongnu.org, Alexandre Iooss , Arnaud Minier , =?UTF-8?q?In=C3=A8s=20Varhol?= , Alistair Francis , Peter Maydell , Samuel Tardieu Subject: [PATCH v3 1/3] hw/intc/armv7m_nvic: add "num-prio-bits" property Date: Sat, 6 Jan 2024 19:15:01 +0100 Message-ID: <20240106181503.1746200-2-sam@rfc1149.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240106181503.1746200-1-sam@rfc1149.net> References: <20240106181503.1746200-1-sam@rfc1149.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.154.227.159; envelope-from=sam@rfc1149.net; helo=zoidberg.rfc1149.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rfc1149.net) X-ZM-MESSAGEID: 1704565005840100014 Content-Type: text/plain; charset="utf-8" Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits. This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless a SOC specifies the number of bits to use, the previous behavior is maintained for backward compatibility. Signed-off-by: Samuel Tardieu Suggested-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 Reviewed-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 50f9a973a2..404a445138 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic =3D { static Property props_nvic[] =3D { /* Number of external IRQ lines (so excluding the 16 internal exceptio= ns) */ DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), + /* + * Number of the maximum priority bits that can be used. 0 means + * to use a reasonable default. + */ + DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0), DEFINE_PROP_END_OF_LIST() }; =20 @@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) /* include space for internal exception vectors */ s->num_irq +=3D NVIC_FIRST_IRQ; =20 - s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + if (s->num_prio_bits =3D=3D 0) { + /* + * If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1 + * and 8 bits otherwise. + */ + s->num_prio_bits =3D arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8= : 2; + } else { + uint8_t min_prio_bits =3D + arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 3 : 2; + if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) { + error_setg(errp, + "num-prio-bits %d is outside " + "NVIC acceptable range [%d-8]", + s->num_prio_bits, min_prio_bits); + return; + } + } =20 /* * This device provides a single memory region which covers the --=20 2.42.0