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Fri, 05 Jan 2024 15:05:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v4 01/17] target/riscv/cpu_cfg.h: remove unused fields Date: Fri, 5 Jan 2024 20:05:30 -0300 Message-ID: <20240105230546.265053-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240105230546.265053-1-dbarboza@ventanamicro.com> References: <20240105230546.265053-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704496163790100001 Content-Type: text/plain; charset="utf-8" user_spec, bext_spec and bext_ver aren't being used. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu_cfg.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 44fb0a9ca8..1c5ab8bd0e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -180,7 +180,6 @@ struct CPUArchState { target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; - target_ulong bext_ver; target_ulong vext_ver; =20 /* RISCVMXL, but uint32_t for vmstate migration */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 780ae6ef17..0612668144 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -140,8 +140,6 @@ struct RISCVCPUConfig { =20 uint32_t pmu_mask; char *priv_spec; - char *user_spec; - char *bext_spec; char *vext_spec; uint16_t vlen; uint16_t elen; --=20 2.43.0