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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/GU8wZxWukKO5ottAlSfJnZgoLvlBp4LP5kVOrDA27o=; b=lQpejTSH75kvREm8BFkLQB4KxmQK9WBo8fbrC/aZxeD8gm8wUXEGaWhcHSbtLHELHGAjuQL3VWoLCs/vbybVTNe+iEVsHbHeA4gD09B2VaQl3ptwPOtrBA/1KSdq4pEvgQzyEG5epnzcjlECok9FiYssLB0qe5Z5ad3CO05SkEUA6/91qJ1gL/iG5SLIpyJ0Lcz6OINMDFUaSF8XJsD9sv8WrfF43CYmW+PZAFNHYlD4d/rwbasgwARERFyPe/dJCw7V9JR5c8fljYiT9EL8BAOZW9GUHmjjiRNkV7xSDnbf8U+a4x7WqQOQol/fesTA/yt/U8NHMvKpY+7J9H6FjQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; From: Sia Jee Heng To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: mst@redhat.com, imammedo@redhat.com, anisinha@redhat.com, peter.maydell@linaro.org, jeeheng.sia@starfivetech.com, shannon.zhaosl@gmail.com, sunilvl@ventanamicro.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com Subject: [RESEND RFC v1 1/2] hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location Date: Fri, 5 Jan 2024 17:06:07 +0800 Message-Id: <20240105090608.5745-2-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240105090608.5745-1-jeeheng.sia@starfivetech.com> References: <20240105090608.5745-1-jeeheng.sia@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SH0PR01CA0007.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:5::19) To BJSPR01MB0561.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:f::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJSPR01MB0561:EE_|BJSPR01MB0755:EE_ X-MS-Office365-Filtering-Correlation-Id: f85dfeb2-3b01-4a37-2c2c-08dc0dcd9890 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2406:e500:4420:2::61d; envelope-from=jeeheng.sia@starfivetech.com; helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1704445668069100005 Content-Type: text/plain; charset="utf-8" RISC-V should also generate the SPCR in a manner similar to ARM. Therefore, instead of replicating the code, relocate this function to the common AML build. Signed-off-by: Sia Jee Heng --- hw/acpi/aml-build.c | 51 ++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 68 +++++++++++++++---------------------- include/hw/acpi/acpi-defs.h | 33 ++++++++++++++++++ include/hw/acpi/aml-build.h | 4 +++ 4 files changed, 115 insertions(+), 41 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index af66bde0f5..1efa534aa8 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1994,6 +1994,57 @@ static void build_processor_hierarchy_node(GArray *t= bl, uint32_t flags, } } =20 +void build_spcr(GArray *table_data, BIOSLinker *linker, + const AcpiSpcrData *f, const char *oem_id, + const char *oem_table_id) +{ + AcpiTable table =3D { .sig =3D "SPCR", .rev =3D 2, .oem_id =3D oem_id, + .oem_table_id =3D oem_table_id }; + + acpi_table_begin(&table, table_data); + /* Interface type */ + build_append_int_noprefix(table_data, f->interface_type, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 3); + /* Base Address */ + build_append_gas(table_data, f->base_addr.id, f->base_addr.width, + f->base_addr.offset, f->base_addr.size, + f->base_addr.addr); + /* Interrupt type */ + build_append_int_noprefix(table_data, f->interrupt_type, 1); + /* IRQ */ + build_append_int_noprefix(table_data, f->pc_interrupt, 1); + /* Global System Interrupt */ + build_append_int_noprefix(table_data, f->interrupt, 4); + /* Baud Rate */ + build_append_int_noprefix(table_data, f->baud_rate, 1); + /* Parity */ + build_append_int_noprefix(table_data, f->parity, 1); + /* Stop Bits */ + build_append_int_noprefix(table_data, f->stop_bits, 1); + /* Flow Control */ + build_append_int_noprefix(table_data, f->flow_control, 1); + /* Terminal Type */ + build_append_int_noprefix(table_data, f->terminal_type, 1); + /* PCI Device ID */ + build_append_int_noprefix(table_data, f->pci_device_id, 2); + /* PCI Vendor ID */ + build_append_int_noprefix(table_data, f->pci_vendor_id, 2); + /* PCI Bus Number */ + build_append_int_noprefix(table_data, f->pci_bus, 1); + /* PCI Device Number */ + build_append_int_noprefix(table_data, f->pci_device, 1); + /* PCI Function Number */ + build_append_int_noprefix(table_data, f->pci_function, 1); + /* PCI Flags */ + build_append_int_noprefix(table_data, f->pci_flags, 4); + /* PCI Segment */ + build_append_int_noprefix(table_data, f->pci_segment, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + + acpi_table_end(linker, &table); +} /* * ACPI spec, Revision 6.3 * 5.2.29 Processor Properties Topology Table (PPTT) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 510ab0dcca..a31f736d1a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -431,48 +431,34 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) * Rev: 1.07 */ static void -build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) +build_spcr_v2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vm= s) { - AcpiTable table =3D { .sig =3D "SPCR", .rev =3D 2, .oem_id =3D vms->oe= m_id, - .oem_table_id =3D vms->oem_table_id }; - - acpi_table_begin(&table, table_data); - - /* Interface Type */ - build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */ - build_append_int_noprefix(table_data, 0, 3); /* Reserved */ - /* Base Address */ - build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 32, 0, 3, - vms->memmap[VIRT_UART].base); - /* Interrupt Type */ - build_append_int_noprefix(table_data, - (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1); - build_append_int_noprefix(table_data, 0, 1); /* IRQ */ - /* Global System Interrupt */ - build_append_int_noprefix(table_data, - vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4); - build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */ - build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity= */ - /* Stop Bits */ - build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1); - /* Flow Control */ - build_append_int_noprefix(table_data, - (1 << 1) /* RTS/CTS hardware flow control */, 1); - /* Terminal Type */ - build_append_int_noprefix(table_data, 0 /* VT100 */, 1); - build_append_int_noprefix(table_data, 0, 1); /* Language */ - /* PCI Device ID */ - build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); - /* PCI Vendor ID */ - build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2); - build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */ - build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */ - build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */ - build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */ - build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */ - build_append_int_noprefix(table_data, 0, 4); /* Reserved */ + AcpiSpcrData serial =3D { + .interface_type =3D 3, /* ARM PL011 UART */ + .base_addr.id =3D AML_AS_SYSTEM_MEMORY, + .base_addr.width =3D 32, + .base_addr.offset =3D 0, + .base_addr.size =3D 3, + .base_addr.addr =3D vms->memmap[VIRT_UART].base, + .interrupt_type =3D (1 << 3),/* Bit[3] ARMH GIC interrupt*/ + .pc_interrupt =3D 0, /* IRQ */ + .interrupt =3D (vms->irqmap[VIRT_UART] + ARM_SPI_BASE), + .baud_rate =3D 3, /* 9600 */ + .parity =3D 0, /* No Parity */ + .stop_bits =3D 1, /* 1 Stop bit */ + .flow_control =3D 1 << 1, /* RTS/CTS hardware flow control */ + .terminal_type =3D 0, /* VT100 */ + .language =3D 0, /* Language */ + .pci_device_id =3D 0xffff, /* not a PCI device*/ + .pci_vendor_id =3D 0xffff, /* not a PCI device*/ + .pci_bus =3D 0, + .pci_device =3D 0, + .pci_function =3D 0, + .pci_flags =3D 0, + .pci_segment =3D 0, + }; =20 - acpi_table_end(linker, &table); + build_spcr(table_data, linker, &serial, vms->oem_id, vms->oem_table_id= ); } =20 /* @@ -930,7 +916,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) } =20 acpi_add_table(table_offsets, tables_blob); - build_spcr(tables_blob, tables->linker, vms); + build_spcr_v2(tables_blob, tables->linker, vms); =20 acpi_add_table(table_offsets, tables_blob); build_dbg2(tables_blob, tables->linker, vms); diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 2b42e4192b..0e6e82b339 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -90,6 +90,39 @@ typedef struct AcpiFadtData { unsigned *xdsdt_tbl_offset; } AcpiFadtData; =20 +typedef struct AcpiGas { + uint8_t id; /* Address space ID */ + uint8_t width; /* Register bit width */ + uint8_t offset; /* Register bit offset */ + uint8_t size; /* Access size */ + uint64_t addr; /* Address */ +} AcpiGas; + +/* SPCR (Serial Port Console Redirection table) */ +typedef struct AcpiSpcrData { + uint8_t interface_type; + uint8_t reserved[3]; + struct AcpiGas base_addr; + uint8_t interrupt_type; + uint8_t pc_interrupt; + uint32_t interrupt; /* Global system interrupt */ + uint8_t baud_rate; + uint8_t parity; + uint8_t stop_bits; + uint8_t flow_control; + uint8_t terminal_type; + uint8_t language; + uint8_t reserved1; + uint16_t pci_device_id; /* Must be 0xffff if not PCI device */ + uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */ + uint8_t pci_bus; + uint8_t pci_device; + uint8_t pci_function; + uint32_t pci_flags; + uint8_t pci_segment; + uint32_t reserved2; +} AcpiSpcrData; + #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) #define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) =20 diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index ff2a310270..44e03e76bd 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -497,4 +497,8 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, const = AcpiFadtData *f, =20 void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, const char *oem_id, const char *oem_table_id); + +void build_spcr(GArray *table_data, BIOSLinker *linker, + const AcpiSpcrData *f, const char *oem_id, + const char *oem_table_id); #endif --=20 2.34.1 From nobody Tue Nov 26 20:21:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=starfivetech.com) ARC-Seal: i=2; a=rsa-sha256; t=1704445666; cv=pass; d=zohomail.com; s=zohoarc; b=E2ANzuuYx18zIDHE/gQrgAlaS7USYhDYtSIfUbXYEEQuJi/OLJuGhUSe3HNYvnI2pU5MaIUQP0yYGn9T40cMa8RaaehRzQwjoYK97lmlAlqa/bn3T47+2nuAZ/moJGEjr+2vp/likY6ZbJMxcwJWEjGE+vd/l2/QPyEOI07tgqg= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704445666; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2406:e500:4420:2::61d; envelope-from=jeeheng.sia@starfivetech.com; helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1704445668023100001 Content-Type: text/plain; charset="utf-8" Generate Serial Port Console Redirection Table (SPCR) for RISC-V virtual machine. Signed-off-by: Sia Jee Heng Reviewed-by: Daniel Henrique Barboza --- hw/riscv/virt-acpi-build.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index d4a02579d6..388b3d1a84 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -174,6 +174,42 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart= _memmap, aml_append(scope, dev); } =20 +/* + * Serial Port Console Redirection Table (SPCR) + * Rev: 1.07 + */ + +static void +build_spcr_rev2(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) +{ + AcpiSpcrData serial =3D { + .interface_type =3D 0, /* 16550 compatible */ + .base_addr.id =3D AML_AS_SYSTEM_MEMORY, + .base_addr.width =3D 32, + .base_addr.offset =3D 0, + .base_addr.size =3D 1, + .base_addr.addr =3D s->memmap[VIRT_UART0].base, + .interrupt_type =3D (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ + .pc_interrupt =3D 0, + .interrupt =3D UART0_IRQ, + .baud_rate =3D 7, /* 15200 */ + .parity =3D 0, + .stop_bits =3D 1, + .flow_control =3D 0, + .terminal_type =3D 3, /* ANSI */ + .language =3D 0, /* Language */ + .pci_device_id =3D 0xffff, /* not a PCI device*/ + .pci_vendor_id =3D 0xffff, /* not a PCI device*/ + .pci_bus =3D 0, + .pci_device =3D 0, + .pci_function =3D 0, + .pci_flags =3D 0, + .pci_segment =3D 0, + }; + + build_spcr(table_data, linker, &serial, s->oem_id, s->oem_table_id); +} + /* RHCT Node[N] starts at offset 56 */ #define RHCT_NODE_ARRAY_OFFSET 56 =20 @@ -555,6 +591,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuil= dTables *tables) acpi_add_table(table_offsets, tables_blob); build_rhct(tables_blob, tables->linker, s); =20 + acpi_add_table(table_offsets, tables_blob); + build_spcr_rev2(tables_blob, tables->linker, s); + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { --=20 2.34.1