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Date: Wed, 3 Jan 2024 18:57:11 +0000 Message-Id: <20240103185716.1790546-2-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103185716.1790546-1-me@deliversmonkey.space> References: <20240103185716.1790546-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704308372634100003 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Zjpm v0.8 is almost frozen and it's much simplier compared to the existing = one: The newer version doesn't allow to specify custom mask or base for masking. Instead it allows only certain options for masking top bits. Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 10 -- target/riscv/cpu.h | 32 +--- target/riscv/cpu_bits.h | 87 ---------- target/riscv/cpu_helper.c | 52 ------ target/riscv/csr.c | 326 ----------------------------------- target/riscv/machine.c | 9 - target/riscv/translate.c | 27 +-- target/riscv/vector_helper.c | 2 +- 8 files changed, 10 insertions(+), 535 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07..1e6571ce99 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -710,13 +710,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) CSR_MSCRATCH, CSR_SSCRATCH, CSR_SATP, - CSR_MMTE, - CSR_UPMBASE, - CSR_UPMMASK, - CSR_SPMBASE, - CSR_SPMMASK, - CSR_MPMBASE, - CSR_MPMMASK, }; =20 for (i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { @@ -891,8 +884,6 @@ static void riscv_cpu_reset_hold(Object *obj) } i++; } - /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |=3D (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); =20 /* * Clear mseccfg and unlock all the PMP entries upon reset. @@ -906,7 +897,6 @@ static void riscv_cpu_reset_hold(Object *obj) pmp_unlock_entries(env); #endif env->xl =3D riscv_cpu_mxl(env); - riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..73f7004936 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -374,18 +374,7 @@ struct CPUArchState { /* True if in debugger mode. */ bool debugger; =20 - /* - * CSRs for PointerMasking extension - */ - target_ulong mmte; - target_ulong mpmmask; - target_ulong mpmbase; - target_ulong spmmask; - target_ulong spmbase; - target_ulong upmmask; - target_ulong upmbase; - - /* CSRs for execution environment configuration */ + /* CSRs for execution enviornment configuration */ uint64_t menvcfg; uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; @@ -393,8 +382,6 @@ struct CPUArchState { target_ulong senvcfg; uint64_t henvcfg; #endif - target_ulong cur_pmmask; - target_ulong cur_pmbase; =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ @@ -543,17 +530,14 @@ FIELD(TB_FLAGS, VILL, 14, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) -/* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) -FIELD(TB_FLAGS, VTA, 20, 1) -FIELD(TB_FLAGS, VMA, 21, 1) +FIELD(TB_FLAGS, VTA, 18, 1) +FIELD(TB_FLAGS, VMA, 19, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 22, 1) +FIELD(TB_FLAGS, ITRIGGER, 20, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, PRIV, 24, 2) -FIELD(TB_FLAGS, AXL, 26, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) +FIELD(TB_FLAGS, PRIV, 22, 2) +FIELD(TB_FLAGS, AXL, 24, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -680,8 +664,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); =20 -void riscv_cpu_update_mask(CPURISCVState *env); - RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ebd7917d49..1c92458a01 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -491,37 +491,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* - * User PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_UMTE 0x4c0 -#define CSR_UPMMASK 0x4c1 -#define CSR_UPMBASE 0x4c2 - -/* - * Machine PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_MMTE 0x3c0 -#define CSR_MPMMASK 0x3c1 -#define CSR_MPMBASE 0x3c2 - -/* - * Supervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_SMTE 0x1c0 -#define CSR_SPMMASK 0x1c1 -#define CSR_SPMBASE 0x1c2 - -/* - * Hypervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_VSMTE 0x2c0 -#define CSR_VSPMMASK 0x2c1 -#define CSR_VSPMBASE 0x2c2 #define CSR_SCOUNTOVF 0xda0 =20 /* Crypto Extension */ @@ -741,11 +710,6 @@ typedef enum RISCVException { #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 -/* General PointerMasking CSR bits */ -#define PM_ENABLE 0x00000001ULL -#define PM_CURRENT 0x00000002ULL -#define PM_INSN 0x00000004ULL - /* Execution environment configuration bits */ #define MENVCFG_FIOM BIT(0) #define MENVCFG_CBIE (3UL << 4) @@ -778,57 +742,6 @@ typedef enum RISCVException { #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE =20 -/* Offsets for every pair of control bits per each priv level */ -#define XS_OFFSET 0ULL -#define U_OFFSET 2ULL -#define S_OFFSET 5ULL -#define M_OFFSET 8ULL - -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) -#define U_PM_INSN (PM_INSN << U_OFFSET) -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) -#define S_PM_INSN (PM_INSN << S_OFFSET) -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET) -#define M_PM_INSN (PM_INSN << M_OFFSET) - -/* mmte CSR bits */ -#define MMTE_PM_XS_BITS PM_XS_BITS -#define MMTE_U_PM_ENABLE U_PM_ENABLE -#define MMTE_U_PM_CURRENT U_PM_CURRENT -#define MMTE_U_PM_INSN U_PM_INSN -#define MMTE_S_PM_ENABLE S_PM_ENABLE -#define MMTE_S_PM_CURRENT S_PM_CURRENT -#define MMTE_S_PM_INSN S_PM_INSN -#define MMTE_M_PM_ENABLE M_PM_ENABLE -#define MMTE_M_PM_CURRENT M_PM_CURRENT -#define MMTE_M_PM_INSN M_PM_INSN -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INS= N | \ - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INS= N | \ - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INS= N | \ - MMTE_PM_XS_BITS) - -/* (v)smte CSR bits */ -#define SMTE_PM_XS_BITS PM_XS_BITS -#define SMTE_U_PM_ENABLE U_PM_ENABLE -#define SMTE_U_PM_CURRENT U_PM_CURRENT -#define SMTE_U_PM_INSN U_PM_INSN -#define SMTE_S_PM_ENABLE S_PM_ENABLE -#define SMTE_S_PM_CURRENT S_PM_CURRENT -#define SMTE_S_PM_INSN S_PM_INSN -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INS= N | \ - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INS= N | \ - SMTE_PM_XS_BITS) - -/* umte CSR bits */ -#define UMTE_U_PM_ENABLE U_PM_ENABLE -#define UMTE_U_PM_CURRENT U_PM_CURRENT -#define UMTE_U_PM_INSN U_PM_INSN -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) - /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ #define ISELECT_IPRIO0 0x30 #define ISELECT_IPRIO15 0x3f diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7e23b34f4..a3d477d226 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -135,61 +135,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *= pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } =20 *pflags =3D flags; } =20 -void riscv_cpu_update_mask(CPURISCVState *env) -{ - target_ulong mask =3D 0, base =3D 0; - RISCVMXL xl =3D env->xl; - /* - * TODO: Current RVJ spec does not specify - * how the extension interacts with XLEN. - */ -#ifndef CONFIG_USER_ONLY - int mode =3D cpu_address_mode(env); - xl =3D cpu_get_xl(env, mode); - if (riscv_has_ext(env, RVJ)) { - switch (mode) { - case PRV_M: - if (env->mmte & M_PM_ENABLE) { - mask =3D env->mpmmask; - base =3D env->mpmbase; - } - break; - case PRV_S: - if (env->mmte & S_PM_ENABLE) { - mask =3D env->spmmask; - base =3D env->spmbase; - } - break; - case PRV_U: - if (env->mmte & U_PM_ENABLE) { - mask =3D env->upmmask; - base =3D env->upmbase; - } - break; - default: - g_assert_not_reached(); - } - } -#endif - if (xl =3D=3D MXL_RV32) { - env->cur_pmmask =3D mask & UINT32_MAX; - env->cur_pmbase =3D base & UINT32_MAX; - } else { - env->cur_pmmask =3D mask; - env->cur_pmbase =3D base; - } -} - #ifndef CONFIG_USER_ONLY =20 /* @@ -721,7 +670,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fde7ce1a53..ea4e1ac6ef 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -483,16 +483,6 @@ static RISCVException hgatp(CPURISCVState *env, int cs= rno) return hmode(env, csrno); } =20 -/* Checks if PointerMasking registers could be accessed */ -static RISCVException pointer_masking(CPURISCVState *env, int csrno) -{ - /* Check if j-ext is present */ - if (riscv_has_ext(env, RVJ)) { - return RISCV_EXCP_NONE; - } - return RISCV_EXCP_ILLEGAL_INST; -} - static int aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { @@ -1355,7 +1345,6 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, env->xl =3D cpu_recompute_xl(env); } =20 - riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -3900,302 +3889,6 @@ static RISCVException read_tinfo(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 -/* - * Functions to access Pointer Masking feature registers - * We have to check if current priv lvl could modify - * csr in given mode - */ -static bool check_pm_current_disabled(CPURISCVState *env, int csrno) -{ - int csr_priv =3D get_field(csrno, 0x300); - int pm_current; - - if (env->debugger) { - return false; - } - /* - * If priv lvls differ that means we're accessing csr from higher priv= lvl, - * so allow the access - */ - if (env->priv !=3D csr_priv) { - return false; - } - switch (env->priv) { - case PRV_M: - pm_current =3D get_field(env->mmte, M_PM_CURRENT); - break; - case PRV_S: - pm_current =3D get_field(env->mmte, S_PM_CURRENT); - break; - case PRV_U: - pm_current =3D get_field(env->mmte, U_PM_CURRENT); - break; - default: - g_assert_not_reached(); - } - /* It's same priv lvl, so we allow to modify csr only if pm.current=3D= =3D1 */ - return !pm_current; -} - -static RISCVException read_mmte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & MMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mmte(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - target_ulong wpri_val =3D val & MMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - /* for machine mode pm.current is hardwired to 1 */ - wpri_val |=3D MMTE_M_PM_CURRENT; - - /* hardwiring pm.instruction bit to 0, since it's not supported yet */ - wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte =3D wpri_val | EXT_STATUS_DIRTY; - riscv_cpu_update_mask(env); - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_smte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & SMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_smte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val =3D val & SMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |=3D (env->mmte & ~SMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_umte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & UMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_umte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val =3D val & UMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |=3D (env->mmte & ~UMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mpmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))= { - env->cur_pmmask =3D val; - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->spmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))= { - env->cur_pmmask =3D val; - if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) { - env->cur_pmmask &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->upmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))= { - env->cur_pmmask =3D val; - if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) { - env->cur_pmmask &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mpmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))= { - env->cur_pmbase =3D val; - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->spmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))= { - env->cur_pmbase =3D val; - if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) { - env->cur_pmbase &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->upmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))= { - env->cur_pmbase =3D val; - if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) { - env->cur_pmbase &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - #endif =20 /* Crypto Extension */ @@ -4800,25 +4493,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore }, =20 - /* User Pointer Masking */ - [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, - [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, - write_upmmask = }, - [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, - write_upmbase = }, - /* Machine Pointer Masking */ - [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write_m= mte }, - [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, - write_mpmmask = }, - [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, - write_mpmbase = }, - /* Supervisor Pointer Masking */ - [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write_s= mte }, - [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, - write_spmmask = }, - [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, - write_spmbase = }, - /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index fdde243e04..860fe56d43 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -164,14 +164,6 @@ static const VMStateDescription vmstate_pointermasking= =3D { .minimum_version_id =3D 1, .needed =3D pointermasking_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINTTL(env.mmte, RISCVCPU), - VMSTATE_UINTTL(env.mpmmask, RISCVCPU), - VMSTATE_UINTTL(env.mpmbase, RISCVCPU), - VMSTATE_UINTTL(env.spmmask, RISCVCPU), - VMSTATE_UINTTL(env.spmbase, RISCVCPU), - VMSTATE_UINTTL(env.upmmask, RISCVCPU), - VMSTATE_UINTTL(env.upmbase, RISCVCPU), - VMSTATE_END_OF_LIST() } }; @@ -267,7 +259,6 @@ static int riscv_cpu_post_load(void *opaque, int versio= n_id) CPURISCVState *env =3D &cpu->env; =20 env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); return 0; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb16..6b4b9a671c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cp= u_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; -/* globals for PM CSRs */ -static TCGv pm_mask; -static TCGv pm_base; =20 /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -106,9 +103,6 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; - /* PointerMasking extension */ - bool pm_mask_enabled; - bool pm_base_enabled; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_address_xl(ctx) =3D=3D MXL_RV32) { + if (get_address_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } =20 return addr; } @@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int= rs1, TCGv offs) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) =3D=3D MXL_RV32) { + if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } return addr; } =20 @@ -1192,8 +1176,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; - ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); - ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; @@ -1325,9 +1307,4 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), "load_val"); - /* Assign PM CSRs to tcg globals */ - pm_mask =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm= mask), - "pmmask"); - pm_base =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm= base), - "pmbase"); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c1c3a4d1ea..8e7a8e80a0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -94,7 +94,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint= 32_t log2_esz) =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { - return (addr & ~env->cur_pmmask) | env->cur_pmbase; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1704308380590100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/csr.c | 11 +++++++++++ target/riscv/machine.c | 6 ++++-- target/riscv/pmp.c | 13 ++++++++++--- target/riscv/pmp.h | 11 ++++++----- 7 files changed, 45 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 73f7004936..bd379ee653 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -102,6 +102,14 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; =20 +/* Enum holds PMM field values for Zjpm v0.8 extension */ +typedef enum { + PMM_FIELD_DISABLED =3D 0, + PMM_FIELD_RESERVED =3D 1, + PMM_FIELD_PMLEN7 =3D 2, + PMM_FIELD_PMLEN16 =3D 3, +} RISCVPmPmm; + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1c92458a01..7cf1049bf4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -715,6 +715,7 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_PMM (3ULL << 32) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -728,11 +729,13 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_PMM MENVCFG_PMM =20 #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PMM MENVCFG_PMM #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..201f8af6ae 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -113,6 +113,9 @@ struct RISCVCPUConfig { bool ext_ssaia; bool ext_sscofpmf; bool ext_smepmp; + bool ext_ssnpm; + bool ext_smnpm; + bool ext_smmpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea4e1ac6ef..a67ba30494 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -527,6 +527,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) if (riscv_cpu_cfg(env)->ext_zkr) { return RISCV_EXCP_NONE; } + if (riscv_cpu_cfg(env)->ext_smmpm) { + return RISCV_EXCP_NONE; + } =20 return RISCV_EXCP_ILLEGAL_INST; } @@ -2030,6 +2033,10 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_ADUE : 0); } + /* Update PMM field only if the value is valid according to Zjpm v0.8 = */ + if (((val & MENVCFG_PMM) >> 32) !=3D PMM_FIELD_RESERVED) { + mask |=3D MENVCFG_PMM; + } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 return RISCV_EXCP_NONE; @@ -2074,6 +2081,10 @@ static RISCVException write_senvcfg(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + /* Update PMM field only if the value is valid according to Zjpm v0.8 = */ + if (((val & SENVCFG_PMM) >> 32) !=3D PMM_FIELD_RESERVED) { + mask |=3D SENVCFG_PMM; + } RISCVException ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 860fe56d43..5e9c5b43ab 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -153,9 +153,8 @@ static const VMStateDescription vmstate_vector =3D { static bool pointermasking_needed(void *opaque) { RISCVCPU *cpu =3D opaque; - CPURISCVState *env =3D &cpu->env; =20 - return riscv_has_ext(env, RVJ); + return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm; } =20 static const VMStateDescription vmstate_pointermasking =3D { @@ -164,6 +163,9 @@ static const VMStateDescription vmstate_pointermasking = =3D { .minimum_version_id =3D 1, .needed =3D pointermasking_needed, .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.mseccfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 162e88a90a..893ccd58d8 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -576,6 +576,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint= 32_t addr_index) void mseccfg_csr_write(CPURISCVState *env, target_ulong val) { int i; + uint64_t mask =3D MSECCFG_MMWP | MSECCFG_MML; + + /* Update PMM field only if the value is valid according to Zjpm v0.8 = */ + if (((val & MSECCFG_PMM) >> 32) !=3D PMM_FIELD_RESERVED) { + mask |=3D MSECCFG_PMM; + } =20 trace_mseccfg_csr_write(env->mhartid, val); =20 @@ -591,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulo= ng val) =20 if (riscv_cpu_cfg(env)->ext_smepmp) { /* Sticky bits */ - val |=3D (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { + val |=3D (env->mseccfg & mask); + if ((val ^ env->mseccfg) & mask) { tlb_flush(env_cpu(env)); } } else { - val &=3D ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); + mask |=3D MSECCFG_RLB; + val &=3D ~(mask); } =20 env->mseccfg =3D val; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 9af8614cd4..b3ca51c26d 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -40,11 +40,12 @@ typedef enum { } pmp_am_t; =20 typedef enum { - MSECCFG_MML =3D 1 << 0, - MSECCFG_MMWP =3D 1 << 1, - MSECCFG_RLB =3D 1 << 2, - MSECCFG_USEED =3D 1 << 8, - MSECCFG_SSEED =3D 1 << 9 + MSECCFG_MML =3D 1 << 0, + MSECCFG_MMWP =3D 1 << 1, + MSECCFG_RLB =3D 1 << 2, + MSECCFG_USEED =3D 1 << 8, + MSECCFG_SSEED =3D 1 << 9, + MSECCFG_PMM =3D 3UL << 32, } mseccfg_field_t; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=baturo.alexey@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704308344447100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 4 +++ target/riscv/cpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bd379ee653..c607a94bba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -672,6 +672,10 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, t= arget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); =20 +bool riscv_cpu_bare_mode(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +int riscv_pm_get_pmlen(RISCVPmPmm pmm); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a3d477d226..4c34e12ee3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -139,6 +139,60 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, *pflags =3D flags; } =20 +RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) +{ + int pmm =3D 0; +#ifndef CONFIG_USER_ONLY + int priv_mode =3D cpu_address_mode(env); + /* Get current PMM field */ + switch (priv_mode) { + case PRV_M: + pmm =3D riscv_cpu_cfg(env)->ext_smmpm ? + get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLE= D; + break; + case PRV_S: + pmm =3D riscv_cpu_cfg(env)->ext_smnpm ? + get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLE= D; + break; + case PRV_U: + pmm =3D riscv_cpu_cfg(env)->ext_ssnpm ? + get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLE= D; + break; + default: + g_assert_not_reached(); + } +#endif + return pmm; +} + +bool riscv_cpu_bare_mode(CPURISCVState *env) +{ + int satp_mode =3D 0; +#ifndef CONFIG_USER_ONLY + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + satp_mode =3D get_field(env->satp, SATP32_MODE); + } else { + satp_mode =3D get_field(env->satp, SATP64_MODE); + } +#endif + return (satp_mode =3D=3D VM_1_10_MBARE); +} + +int riscv_pm_get_pmlen(RISCVPmPmm pmm) +{ + switch (pmm) { + case PMM_FIELD_DISABLED: + return 0; + case PMM_FIELD_PMLEN7: + return 7; + case PMM_FIELD_PMLEN16: + return 16; + default: + g_assert_not_reached(); + } + return -1; +} + #ifndef CONFIG_USER_ONLY =20 /* --=20 2.34.1 From nobody Tue Nov 26 20:26:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id ep16-20020a1709069b5000b00a27d5e9b3ebsm3897915ejc.105.2024.01.03.10.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 10:57:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704308255; x=1704913055; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=geTzYZ7pnQRsHsbIJKqtgIpr5fN2iDhGOj5vL6bsg7c=; b=jtxegwRhPgwzxPKtMN0lk+1UQ2gHxsjVHMUA//pugqxvl/+T4Gliv1WUenBXPwXb42 5tW2CRLUvYBB3iFYcBlF0wZXgUbVAFWjt/8wDBv+wMEIzlvsnc9jbVfJvG6EumHi5FEW +30Cofii+q20S3+3JgYPxs5z37ZQLdY34O54UbgP5SljDIYhrNSylZSsXQPkRUU5Fh9s 8md+SmABsMkLt3tVPjhx9qGLgA88Jfi3s6+clg5p6izhfsB+p//z/G1zNA3PHh/rbOLe RPhDPEpIcjT9UParOFFFZQ1Y1lzaK3h+QY26Pllt30QvRnowf9cXWr07XTixrI+g7yeg WyFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704308255; x=1704913055; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=geTzYZ7pnQRsHsbIJKqtgIpr5fN2iDhGOj5vL6bsg7c=; b=b2crIxGOOY6ZyJJ9CSl42OmClhnm1MEX59GWIl4wJbcwx4P0LwCCBAN8RBjXnX5ARR byjEkFE11Co2anSNhsIaVeI5FsaZmpYyUbb8xfLjbZGlxvr+AnTtogsRJCngjhMb1zwk iOQJH4ixWa6ve/7cojdqqeRIgViortgjGmxhl9wb/Oom9e3yKAzX71CXnHnm+Enz33yx scdno1v/sGLMt7o7J+VJP8MmmvqXZe+u6Tz5PwU04sc3QoCViSC+nzMHB4kxv6lVslPZ xmSsf7a6fLIPanYN+Y3gm4M1/iiHuNP892s/LpguTir/rxmec2lMqJxIDGmwXFOKp3Ff KNiQ== X-Gm-Message-State: AOJu0YyuVrW6bOeF25BNXbizx0DcMatFSCGJ0M+fxsO63kYNBYcrWNM4 26BfvkKF3u6UJavuvn7RwH0= X-Google-Smtp-Source: AGHT+IGeoy8XhYrtjRvKtAdi4/Q8AwImFeufoVp9TqAeg2oYyX+h9rUwBKf0v0CImAP0yK7byphKew== X-Received: by 2002:a17:906:4ad5:b0:a26:997e:fc9e with SMTP id u21-20020a1709064ad500b00a26997efc9emr1513758ejt.3.1704308255469; Wed, 03 Jan 2024 10:57:35 -0800 (PST) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 4/6] target/riscv: Add pointer masking tb flags Date: Wed, 3 Jan 2024 18:57:14 +0000 Message-Id: <20240103185716.1790546-5-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240103185716.1790546-1-me@deliversmonkey.space> References: <20240103185716.1790546-1-me@deliversmonkey.space> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704308340454100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 11 +++++++++++ 3 files changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c607a94bba..4df160494f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -546,6 +546,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1) FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) FIELD(TB_FLAGS, PRIV, 22, 2) FIELD(TB_FLAGS, AXL, 24, 2) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 26, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4c34e12ee3..b8d8a622f3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; + bool pm_signext =3D !riscv_cpu_bare_mode(env); =20 *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6b4b9a671c..8ac2819fa5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -103,6 +103,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* actual address width */ + uint8_t addr_width; + bool addr_signed; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1176,6 +1179,14 @@ static void riscv_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; + if (get_xl(ctx) =3D=3D MXL_RV32) { + ctx->addr_width =3D 32; + ctx->addr_signed =3D false; + } else { + int pm_pmm =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); + ctx->addr_width =3D 64 - riscv_pm_get_pmlen(pm_pmm); + ctx->addr_signed =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); + } ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; --=20 2.34.1 From nobody Tue Nov 26 20:26:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1704308304; cv=none; d=zohomail.com; s=zohoarc; b=dJ/fC9PENr0Tkgam83cOgHOGh4opR7nPBRwoA+I0bYlBc9pir7wBFrmK2HtyJgX4TXeu1k8oy53e0BVJwmQ04rHD1gUK2tx0Y37+K8pk8gWRGVV5Y2E8Fjn5PjPt3+zbdrIiQo9vzCgAuiYvyimgDlMN+rwcxd843E+DWvnUyEQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704308304; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:Message-Id:Reply-To:To; bh=i2MaYTcakVdiegE/kAzxB9T4Enfs08wEwhHtLGdW1Uc=; b=RyfxBZWI6RNx7CF6+k8BspUrX4Lv4dypazT25+q0xWJMV3bMpARzrzRt6nmaetvvcVaB2GZjg88j7l+/c/YoNLf4lKznsLWVSUQYUWLrKBRB7EIli6VZRu1oMUL9okjOAhYtRQpGi+EeSG1gH5fEwzrhiQgCSNag8dVjbDLTRak= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17043083044573.712787738767929; Wed, 3 Jan 2024 10:58:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL6Qy-0005Bk-UX; Wed, 03 Jan 2024 13:57:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL6Qu-0005A4-Hn; Wed, 03 Jan 2024 13:57:40 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL6Qs-00043a-Q7; Wed, 03 Jan 2024 13:57:40 -0500 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a27874c861aso472444366b.1; Wed, 03 Jan 2024 10:57:38 -0800 (PST) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. [188.255.126.251]) by smtp.gmail.com with ESMTPSA id ep16-20020a1709069b5000b00a27d5e9b3ebsm3897915ejc.105.2024.01.03.10.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 10:57:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704308257; x=1704913057; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i2MaYTcakVdiegE/kAzxB9T4Enfs08wEwhHtLGdW1Uc=; b=bYpJQt7nDG7HpvCfCeFo66+mMAGDzn0srZ6un77foA8HqSlmlk8WbPRw2+inMzPAUx 4FtN0ghJGaX++utFAwonaQCg53fVVSRD1gNtanJfru+zcPMaO+UtNChsGPI0Ua1kGRyd JB9qWTXw8w5ipTiI4tedf7aowsJIBlcp0z2Vjn4LsRY2wtT5diRgUeEMYDoXj/T9+b9y X6O1yxLrv5nHkwn7XlNowqtNDLRzZhihUKi0T6XyIexCNjtstK46PfKAJVG/TBRnjrQc Wxz0NLl28mQaudWc9wmRY+z25lfxE27+B2MCASt3HqXTXtGpa4d8mLz3Rqc6RwPmC98h bmAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704308257; x=1704913057; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704308306648100003 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo Reviewed-by: Richard Henderson --- target/riscv/translate.c | 12 ++++++++---- target/riscv/vector_helper.c | 12 ++++++++++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8ac2819fa5..457de381c7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -579,8 +579,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) =3D=3D MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width); } =20 return addr; @@ -593,8 +595,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int= rs1, TCGv offs) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) =3D=3D MXL_RV32) { - tcg_gen_ext32u_tl(addr, addr); + if (ctx->addr_signed) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width); + } else { + tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width); } return addr; } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8e7a8e80a0..b91c21d1f4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc, uin= t32_t log2_esz) =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { + RISCVPmPmm pmm =3D riscv_pm_get_pmm(env); + if (pmm =3D=3D PMM_FIELD_DISABLED) + return addr; + int pmlen =3D riscv_pm_get_pmlen(pmm); + bool signext =3D !riscv_cpu_bare_mode(env); + addr =3D addr << pmlen; + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr =3D (target_long)addr >> pmlen; + } else { + addr =3D addr >> pmlen; + } return addr; } =20 --=20 2.34.1 From nobody Tue Nov 26 20:26:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1704308306; cv=none; d=zohomail.com; s=zohoarc; b=PhU8fMbSTILHiT8ZHZn+2HZLEeRuuwHW4BWC3w1B88MRqXcQ+B3KJIkwx5pXHoiyKabJSHRm2hxzYtaMLMgMG5IJS0my3xG7B9wDH1HFEsM650I+PzGOrR7V5uB3I8eDZuvZbuuIcZ5js5kynJkhZ6KAsNBAJRxslo3sMQgCSXY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1704308308450100007 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e6571ce99..13389ddc55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm), + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm), + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1337,6 +1340,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { =20 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), =20 + /* Zjpm v0.8 extensions */ + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false), + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), + MULTI_EXT_CFG_BOOL("zca", ext_zca, false), MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false), MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false), --=20 2.34.1