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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303633; x=1704908433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cz+jeKfAbDjCYD0ym8saUo72Sdfqs84e9WmM8BUjwrU=; b=cF2M+Jbwj39s6BqeSCZAUUhURpVNCT1yMDBa1NK/I05AzIrhXxhGu+FvH4EwTBGS+P UjXI6tPdLZ2mlLRqMMwRhy5eaEuegwsA8CTULry9gwWsT/IsfgrQ7IcLHOZPH5vB3mG4 dLKe71vIDHfehqI9kNgcBKe6IRHEzha1fMr7WCOX8RGeqF81D9K/l4lLbTiVVL3gYAmM AgiJ3AZyEjT5rkYmCsH1Cb+Fdmxr/xc4w+NAmdZwrCeyI3MUlcucE6U70VdlPV4yH04z mQsxaqahIOeeuGoNgwZetn3jhJ/Tv27MiW3FiapD2Onay/xkn7ZB5gVZHhBXwB8IHt6Y 7IcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303633; x=1704908433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cz+jeKfAbDjCYD0ym8saUo72Sdfqs84e9WmM8BUjwrU=; b=UdVmh98o0qyFPSN1YM8o39p34N8ytb4XXZcbvAkHG+VPtWgV5VCOtLWA2J9IO35MxA eZi10IR+G4qDkNWehcoKOdG2cxbxWM9mCPQQnFBgwz9QcHooqsS3OivEJ8T8YYy/NEcs 4Q/GoZAXmE7SZIZLgtB9IF609cuxTaRu855BMzxdKaMiN88o/RJAmPjQo62PW7NHT8tR 3b5TuG0SNfAdRLmWQIB0LJ8O1Kl/b6uOkSJit7JndkEUl01zuVGRThBPsvypdfHbNAj4 nlrm+GIRAt+ulfioEeAREapmyfDNG15pPOsFtKEwjWKu/SniDq3pfWdMlzf5uy9pPDnO 5smQ== X-Gm-Message-State: AOJu0YzDhyd41+MdnsXqqGip2pzOFWM0Mlcl84DEvao25ZkQ8Xsn3XyP 6rEqqZGIwERB9bAFCfzglxIQ3NW7mlgFstxggMv8BdTDrcT0uw== X-Google-Smtp-Source: AGHT+IH8RBd0Oy6dDeXQTx9unafqxpxaEpNLMBbFRBJNSMM+I88VcaEcTcdjFxNqHXHNFc3UfuUPpw== X-Received: by 2002:a62:e805:0:b0:6d9:a014:ca4a with SMTP id c5-20020a62e805000000b006d9a014ca4amr15593638pfi.51.1704303633405; Wed, 03 Jan 2024 09:40:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 03/16] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:00 -0300 Message-ID: <20240103174013.147279-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704304012756100001 Content-Type: text/plain; charset="utf-8" Every property in riscv_cpu_options[] will be migrated to riscv_cpu_properties[]. This will make their default values init earlier, allowing cpu_init() functions to overwrite them. We'll also implement common getters and setters that both accelerators will use, allowing them to share validations that TCG is doing. At the same time, some options (namely 'vlen', 'elen' and the cache blocksizes) need a way of tracking if the user set a value for them. This is benign for TCG since the cost of always validating these values are small, but for KVM we need syscalls to read the host values to make the validations, thus knowing whether the user didn't touch the values makes a difference. We'll track user setting for these properties using a hash, like we do in the TCG driver. All riscv cpu options will update this hash in case the user sets it. The KVM driver will use this hash to minimize the amount of syscalls done. For now, both 'pmu-mask' and 'pmu-num' shouldn't be changed for vendor CPUs. The existing setter for 'pmu-num' is changed to add this restriction. New getters and setters are required for 'pmu-mask' While we're at it, add a 'static' modifier to 'prop_pmu_num' since we're not exporting it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 96 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 89 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 65cfa6c740..e90b70c0a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -53,6 +53,15 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF,= RVD, RVV, #define BYTE(x) (x) #endif =20 +/* Hash that stores general user set numeric options */ +static GHashTable *general_user_opts; + +static void cpu_option_add_user_setting(const char *optname, uint32_t valu= e) +{ + g_hash_table_insert(general_user_opts, (gpointer)optname, + GUINT_TO_POINTER(value)); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1218,11 +1227,15 @@ static void riscv_cpu_post_init(Object *obj) =20 static void riscv_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ =20 + general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); + /* * The timer and performance counters extensions were supported * in QEMU before they were added as discrete extensions in the @@ -1232,6 +1245,9 @@ static void riscv_cpu_init(Object *obj) */ RISCV_CPU(obj)->cfg.ext_zicntr =3D true; RISCV_CPU(obj)->cfg.ext_zihpm =3D true; + + /* Default values for non-bool cpu properties */ + cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); } =20 typedef struct misa_ext_info { @@ -1431,26 +1447,51 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_e= xts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static bool riscv_cpu_is_vendor(Object *obj) +{ + return !riscv_cpu_is_generic(obj); +} + +static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, + Error **errp) +{ + g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); + error_setg(errp, "CPU '%s' does not allow changing the value of '%s'", + cpuname, propname); +} + static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint8_t pmu_num; + uint8_t pmu_num, curr_pmu_num; + uint32_t pmu_mask; =20 visit_type_uint8(v, name, &pmu_num, errp); =20 + curr_pmu_num =3D ctpop32(cpu->cfg.pmu_mask); + + if (pmu_num !=3D curr_pmu_num && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, curr_pmu_num); + return; + } + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } =20 if (pmu_num =3D=3D 0) { - cpu->cfg.pmu_mask =3D 0; + pmu_mask =3D 0; } else { - cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, pmu_num); + pmu_mask =3D MAKE_64BIT_MASK(3, pmu_num); } =20 warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); + cpu->cfg.pmu_mask =3D pmu_mask; + cpu_option_add_user_setting("pmu-mask", pmu_mask); } =20 static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, @@ -1462,16 +1503,54 @@ static void prop_pmu_num_get(Object *obj, Visitor *= v, const char *name, visit_type_uint8(v, name, &pmu_num, errp); } =20 -const PropertyInfo prop_pmu_num =3D { +static const PropertyInfo prop_pmu_num =3D { .name =3D "pmu-num", .get =3D prop_pmu_num_get, .set =3D prop_pmu_num_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK= (3, 16)), - {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ +static void prop_pmu_mask_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint32_t value; + uint8_t pmu_num; + + visit_type_uint32(v, name, &value, errp); + + if (value !=3D cpu->cfg.pmu_mask && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %x\n", + name, cpu->cfg.pmu_mask); + return; + } + + pmu_num =3D ctpop32(value); + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; + } =20 + cpu_option_add_user_setting(name, value); + cpu->cfg.pmu_mask =3D value; +} + +static void prop_pmu_mask_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint8_t pmu_mask =3D RISCV_CPU(obj)->cfg.pmu_mask; + + visit_type_uint8(v, name, &pmu_mask, errp); +} + +static const PropertyInfo prop_pmu_mask =3D { + .name =3D "pmu-mask", + .get =3D prop_pmu_mask_get, + .set =3D prop_pmu_mask_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 @@ -1490,6 +1569,9 @@ Property riscv_cpu_options[] =3D { static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 + {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, + {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0