From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704304124; cv=none; d=zohomail.com; s=zohoarc; b=cnIrtUyNo/inr6hIpft9MEU5Jmk9IpQ5s7NkeJwKYIH4abrOtDwFVupmErIrbgGpLYMpf+HAt6VaVM2Tbhq6dhlEFKQU8oz0Guiu7oAj0fIS2mZHGHKrtlbapO/+l/bNpuT75oqIKHjmQ5uIjxz2GtxxxBTkBJYoy/QrQEEWavU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704304124; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iPGSESp/CUCLZoNx8N16PKLb5QqnmdpX6vsDgGj1+cM=; b=lSjji6vtKsRg4wXFEAe7lzWmE7gEGjxeECDqzX51dwFkkkeUF7spux6tflU2PKYPFJ1suzvK+IAF9toe6yYnbP0beQU36JBCotRb09R8h3QkYJ7sQj/ze4YTLtjOjMTRLR+ZTAIHBFXxKsT5KjfV6SlQfGgiw0vscE3918M1BQ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704304124533514.0277343667111; Wed, 3 Jan 2024 09:48:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5ES-0002WK-GQ; Wed, 03 Jan 2024 12:40:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5EF-0002EH-6L for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:31 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5EC-0001Uq-Al for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:30 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6d9f94b9186so4670499b3a.0 for ; Wed, 03 Jan 2024 09:40:27 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303626; x=1704908426; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iPGSESp/CUCLZoNx8N16PKLb5QqnmdpX6vsDgGj1+cM=; b=MVlP/4tJ9sJ6AY0eVxEzUq6kIKK4SjVbhTT1766iVu1MjzFMKNd7I37qS12ZImmqLk ymJx1W07N1eQnBT6wqy8aMK6SIHQhG4O7SUaREyLL5LOmTzOMivYU5M+axStJfoFvZPb 5KSYS2gnapSn831qpiWcdcnJF2jSSlQ7h63KXrYMCKn6dUAZTIUbkOu3BS7qZ2YZpRw4 O89xIXy7yDAEaQqgzdacvptirlracfMqSFbGV2z7H+q8YoG0mTy4wYTjIQEeepCtp3hi 2FeSgnVw8WVoYF+EzvYW/MCxNehvapZGwLG0s3pjmeORH2iy5MjP1K95iRy+PGEfFVkf MsGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303626; x=1704908426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iPGSESp/CUCLZoNx8N16PKLb5QqnmdpX6vsDgGj1+cM=; b=RlZoA/5Q3o1MTxQEws+SsJdrMbxw2TzIiQypeZjcKZM+boXr0NJfJGIkAqffoeH/xj OSxlzho3Bd6QrCB08Ep1mJk6SJEoYcW8dgMt/64YEtATadqBFC81oMHT+3iX8C+Xm2Hg L6tqYF16QHinpjxUvHbiZg81/VKqnbvZP/2/6UlB7wLsiylw9piBzd5t7/6/XiPL97lD GjBpUucGivJoZFxA7hiPE/mo7H7ZSpSl0p7lyVMLfHPrGJnZRAblhpB0rPz85EsF0XUB B0BgMU/GW8z09O1qd5v8UlWDOTXwR7yufMirhOMzqHRnuFZjPGeDpOn3d7SdmctBKYTA Kqxw== X-Gm-Message-State: AOJu0Yw8h0h/Y8wd4zSBXIr4ADC8gj2RCE3j/vaJvwHOB/dJJs2Jdum4 yky2xL9CGKDdpDN/F6ULoQMonp2b3SmT/eCkrs5/cMotIDn8Ew== X-Google-Smtp-Source: AGHT+IF6wVreYAvLZQxLZEH57HIJpgt9VScSAwYd7YJD2xnpPMQmb6tRDJuUMnZ1g0/9CdBFgv17Bg== X-Received: by 2002:a05:6a00:90a4:b0:6d9:b173:4f9b with SMTP id jo36-20020a056a0090a400b006d9b1734f9bmr8975770pfb.38.1704303626046; Wed, 03 Jan 2024 09:40:26 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 01/16] target/riscv/cpu_cfg.h: remove unused fields Date: Wed, 3 Jan 2024 14:39:58 -0300 Message-ID: <20240103174013.147279-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704304125423100001 Content-Type: text/plain; charset="utf-8" user_spec, bext_spec and bext_ver aren't being used. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu_cfg.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..40c96a32cc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -164,7 +164,6 @@ struct CPUArchState { target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; - target_ulong bext_ver; target_ulong vext_ver; =20 /* RISCVMXL, but uint32_t for vmstate migration */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..c67a8731d3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,8 +136,6 @@ struct RISCVCPUConfig { =20 uint32_t pmu_mask; char *priv_spec; - char *user_spec; - char *bext_spec; char *vext_spec; uint16_t vlen; uint16_t elen; --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303695; cv=none; d=zohomail.com; s=zohoarc; b=Z2GkkLSgZooMvrMrJfwcd9RumeJMeX3exdG1wNzPjmWbvxQhyBLUP1f4C2V4U8/y4W9dC932Ix4S5KeODWaiZyqwYpb/wbjl6t1J3s9oSCLVch3Jqfggd2JIh/MdxPsL+OKZVP1/TwhkK7VypiaSRqMFqcj9m41QPjVVw1icn4A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303695; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=afT5wE04eaPASU0VvwKt04xd7mUQk2Pdh4so599y5Fs=; b=jrMBblUqEg7xfGYF1n2jErqVt+rGU4+1yROGS+Q3RQ27j2PfLa/aDcrl2/2URjUB57Emx8/e9iE42/wPIc/flNCJoM8SKifTvruiIvGNDNfc+e8vnSdIe5ZiRewpZBWD9sRAgebNT2nnOr0OK8vEWVttSUvKur8dDOtfwFi50vI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704303695516866.6573459577394; Wed, 3 Jan 2024 09:41:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5EY-0002z6-68; Wed, 03 Jan 2024 12:40:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5EI-0002Lv-3m for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:36 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5EG-0001Wn-1g for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:33 -0500 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6d9bec20980so2787743b3a.2 for ; Wed, 03 Jan 2024 09:40:31 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303630; x=1704908430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=afT5wE04eaPASU0VvwKt04xd7mUQk2Pdh4so599y5Fs=; b=Lj5cMSGOaHW8UA3Px1FW8//5ckIUtPqLUd6NTSmfmVstbQH+QQwUW+kFHEdTZWz+j3 VmZaglOQOiZHtKZEfIwti4luH7moX6+T6bU0lwL3fUGrJskHLqKnNi/mv1+ZkH59K+gN KUDOOcea4BItoM0GcPcpRAwOD91NeSwk000XHWeB9lldm91JPwPyrybphQEzFWfcxWcs PQdOLCg1E9qptizSwIReXZM0uErnLb8RyvD3FSj1W5Py1AjD+z/F/wN4B1+03t3lcfzj aCMjhA51xuQO7oIJXsZhiZl/U3DU2XfTs6indyg5cXyDPHcKHAgybeSKxXkhbUf8RPbh Gy0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303630; x=1704908430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=afT5wE04eaPASU0VvwKt04xd7mUQk2Pdh4so599y5Fs=; b=nqSVPOTtwmNeZ5HQIepLzAyJ0iHaKqFz1bQbkCjHbnh3n/l4fyrUORXOY6va7o76QJ Saso0gw7xJ6/b+Dza/n3rvLus1n9JGSLYs0UVU4MLIcgnd9e8abkVjXLbBhRYA3rXmwj o+Kf7KKX5z9webGu//1tLjyKN6q5sYQeIm1gczpBiBX93HO1ZM+rU8YB9uJk0WjphokN 8ueL0SvNGW0GvTgE8Phh7Jqul15wfIzIkM2qWYf4y9JYoshqYZN+q+gg/l9aGr9GWF34 wjuojAOIpLquy+J2rltkucoWpoa76ZfRZFwvZFyWRtSeM6n35VbVmQLIi6EHXMJ8SBVV TcaQ== X-Gm-Message-State: AOJu0Ywb5syUXkU7YP5d29+j/SiCatgLa+r2LVEW49dJTzjKzYnPwLuB y/KMifqODriSJlRL2YEAESAYEnavGsQubopwuB5tIHrhQ+e/lQ== X-Google-Smtp-Source: AGHT+IFVQX8RXXeGoiis/hniof6sItZpeppfaAoHdamXjEmG3f1Pe37PA95+rX2a9+84VtmK0uo3kg== X-Received: by 2002:a05:6a20:992:b0:196:9f89:29ba with SMTP id e18-20020a056a20099200b001969f8929bamr2778528pzb.45.1704303629736; Wed, 03 Jan 2024 09:40:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 02/16] target/riscv: make riscv_cpu_is_generic() public Date: Wed, 3 Jan 2024 14:39:59 -0300 Message-ID: <20240103174013.147279-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303697358100003 Content-Type: text/plain; charset="utf-8" We'll use this function in target/riscv/cpu.c to implement setters that won't allow vendor CPU options to be changed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 5 ----- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70bf10aa7c..65cfa6c740 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,11 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ex= t_offset, bool en) *ext_enabled =3D en; } =20 +bool riscv_cpu_is_generic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 40c96a32cc..bf69cb9a27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -756,6 +756,7 @@ enum riscv_pmu_event_idx { void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +bool riscv_cpu_is_generic(Object *cpu_obj); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a34..a09300e908 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -658,11 +658,6 @@ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) =3D=3D NU= LL; } =20 -static bool riscv_cpu_is_generic(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - /* * We'll get here via the following path: * --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704304011; cv=none; d=zohomail.com; s=zohoarc; b=IaqVQXLr/wXEhC6fg19B2PVx0k7IVPOqcaasBOibVQvrfBASXA7W9DuZIaK0neMsInXZUSp5FSS+qJziWK14ViqAhrcUtg8sv+gTwizE/CR+5ZPOOldBG1eJYnPtqiZccRdlrNowM6hz9TBVCVFpUdYxlf4OoC+rH2MVh2uIVhQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704304011; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cz+jeKfAbDjCYD0ym8saUo72Sdfqs84e9WmM8BUjwrU=; b=KLBnwIEfKnaR0n5qIOzteQwaVju4/YRAKjiqBiG1+Jw2IQbvUevw4En92TCsIv3wbNLgKHfYhEgI+9TZO+Iyz4vNtM6hPGj/CeyQq+qxu1PCmR4WgixZNz0Qog44ThGzh3uzFV4oVxI1hJNuA3wFu73xvlePAqNxGVO2VM8ScDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704304011517690.810134653022; Wed, 3 Jan 2024 09:46:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5EX-0002re-JL; Wed, 03 Jan 2024 12:40:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5EM-0002Sv-P6 for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:40 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5EK-0001ZB-Er for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:38 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6d9af1f12d5so6489927b3a.3 for ; Wed, 03 Jan 2024 09:40:35 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303633; x=1704908433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cz+jeKfAbDjCYD0ym8saUo72Sdfqs84e9WmM8BUjwrU=; b=cF2M+Jbwj39s6BqeSCZAUUhURpVNCT1yMDBa1NK/I05AzIrhXxhGu+FvH4EwTBGS+P UjXI6tPdLZ2mlLRqMMwRhy5eaEuegwsA8CTULry9gwWsT/IsfgrQ7IcLHOZPH5vB3mG4 dLKe71vIDHfehqI9kNgcBKe6IRHEzha1fMr7WCOX8RGeqF81D9K/l4lLbTiVVL3gYAmM AgiJ3AZyEjT5rkYmCsH1Cb+Fdmxr/xc4w+NAmdZwrCeyI3MUlcucE6U70VdlPV4yH04z mQsxaqahIOeeuGoNgwZetn3jhJ/Tv27MiW3FiapD2Onay/xkn7ZB5gVZHhBXwB8IHt6Y 7IcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303633; x=1704908433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cz+jeKfAbDjCYD0ym8saUo72Sdfqs84e9WmM8BUjwrU=; b=UdVmh98o0qyFPSN1YM8o39p34N8ytb4XXZcbvAkHG+VPtWgV5VCOtLWA2J9IO35MxA eZi10IR+G4qDkNWehcoKOdG2cxbxWM9mCPQQnFBgwz9QcHooqsS3OivEJ8T8YYy/NEcs 4Q/GoZAXmE7SZIZLgtB9IF609cuxTaRu855BMzxdKaMiN88o/RJAmPjQo62PW7NHT8tR 3b5TuG0SNfAdRLmWQIB0LJ8O1Kl/b6uOkSJit7JndkEUl01zuVGRThBPsvypdfHbNAj4 nlrm+GIRAt+ulfioEeAREapmyfDNG15pPOsFtKEwjWKu/SniDq3pfWdMlzf5uy9pPDnO 5smQ== X-Gm-Message-State: AOJu0YzDhyd41+MdnsXqqGip2pzOFWM0Mlcl84DEvao25ZkQ8Xsn3XyP 6rEqqZGIwERB9bAFCfzglxIQ3NW7mlgFstxggMv8BdTDrcT0uw== X-Google-Smtp-Source: AGHT+IH8RBd0Oy6dDeXQTx9unafqxpxaEpNLMBbFRBJNSMM+I88VcaEcTcdjFxNqHXHNFc3UfuUPpw== X-Received: by 2002:a62:e805:0:b0:6d9:a014:ca4a with SMTP id c5-20020a62e805000000b006d9a014ca4amr15593638pfi.51.1704303633405; Wed, 03 Jan 2024 09:40:33 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 03/16] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:00 -0300 Message-ID: <20240103174013.147279-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704304012756100001 Content-Type: text/plain; charset="utf-8" Every property in riscv_cpu_options[] will be migrated to riscv_cpu_properties[]. This will make their default values init earlier, allowing cpu_init() functions to overwrite them. We'll also implement common getters and setters that both accelerators will use, allowing them to share validations that TCG is doing. At the same time, some options (namely 'vlen', 'elen' and the cache blocksizes) need a way of tracking if the user set a value for them. This is benign for TCG since the cost of always validating these values are small, but for KVM we need syscalls to read the host values to make the validations, thus knowing whether the user didn't touch the values makes a difference. We'll track user setting for these properties using a hash, like we do in the TCG driver. All riscv cpu options will update this hash in case the user sets it. The KVM driver will use this hash to minimize the amount of syscalls done. For now, both 'pmu-mask' and 'pmu-num' shouldn't be changed for vendor CPUs. The existing setter for 'pmu-num' is changed to add this restriction. New getters and setters are required for 'pmu-mask' While we're at it, add a 'static' modifier to 'prop_pmu_num' since we're not exporting it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 96 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 89 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 65cfa6c740..e90b70c0a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -53,6 +53,15 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF,= RVD, RVV, #define BYTE(x) (x) #endif =20 +/* Hash that stores general user set numeric options */ +static GHashTable *general_user_opts; + +static void cpu_option_add_user_setting(const char *optname, uint32_t valu= e) +{ + g_hash_table_insert(general_user_opts, (gpointer)optname, + GUINT_TO_POINTER(value)); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1218,11 +1227,15 @@ static void riscv_cpu_post_init(Object *obj) =20 static void riscv_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ =20 + general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); + /* * The timer and performance counters extensions were supported * in QEMU before they were added as discrete extensions in the @@ -1232,6 +1245,9 @@ static void riscv_cpu_init(Object *obj) */ RISCV_CPU(obj)->cfg.ext_zicntr =3D true; RISCV_CPU(obj)->cfg.ext_zihpm =3D true; + + /* Default values for non-bool cpu properties */ + cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); } =20 typedef struct misa_ext_info { @@ -1431,26 +1447,51 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_e= xts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static bool riscv_cpu_is_vendor(Object *obj) +{ + return !riscv_cpu_is_generic(obj); +} + +static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, + Error **errp) +{ + g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); + error_setg(errp, "CPU '%s' does not allow changing the value of '%s'", + cpuname, propname); +} + static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint8_t pmu_num; + uint8_t pmu_num, curr_pmu_num; + uint32_t pmu_mask; =20 visit_type_uint8(v, name, &pmu_num, errp); =20 + curr_pmu_num =3D ctpop32(cpu->cfg.pmu_mask); + + if (pmu_num !=3D curr_pmu_num && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, curr_pmu_num); + return; + } + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } =20 if (pmu_num =3D=3D 0) { - cpu->cfg.pmu_mask =3D 0; + pmu_mask =3D 0; } else { - cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, pmu_num); + pmu_mask =3D MAKE_64BIT_MASK(3, pmu_num); } =20 warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); + cpu->cfg.pmu_mask =3D pmu_mask; + cpu_option_add_user_setting("pmu-mask", pmu_mask); } =20 static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, @@ -1462,16 +1503,54 @@ static void prop_pmu_num_get(Object *obj, Visitor *= v, const char *name, visit_type_uint8(v, name, &pmu_num, errp); } =20 -const PropertyInfo prop_pmu_num =3D { +static const PropertyInfo prop_pmu_num =3D { .name =3D "pmu-num", .get =3D prop_pmu_num_get, .set =3D prop_pmu_num_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK= (3, 16)), - {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ +static void prop_pmu_mask_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint32_t value; + uint8_t pmu_num; + + visit_type_uint32(v, name, &value, errp); + + if (value !=3D cpu->cfg.pmu_mask && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %x\n", + name, cpu->cfg.pmu_mask); + return; + } + + pmu_num =3D ctpop32(value); + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; + } =20 + cpu_option_add_user_setting(name, value); + cpu->cfg.pmu_mask =3D value; +} + +static void prop_pmu_mask_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint8_t pmu_mask =3D RISCV_CPU(obj)->cfg.pmu_mask; + + visit_type_uint8(v, name, &pmu_mask, errp); +} + +static const PropertyInfo prop_pmu_mask =3D { + .name =3D "pmu-mask", + .get =3D prop_pmu_mask_get, + .set =3D prop_pmu_mask_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 @@ -1490,6 +1569,9 @@ Property riscv_cpu_options[] =3D { static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 + {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, + {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303637; x=1704908437; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iuIlMixa+qWdIu7SpCSQCDmDPoiwKpmn6qm/naO42AI=; b=hnjRefqabqwKnVk7xXTmFNTPnAvUGvRwPBuOeYoMLek/9VKclXH6RnEKzylRnH8oms 5sgvNTxCwaL8uYH2uzb5asDf5EyHdTkfSNKBIeKjgHX5YdU0N0AHHnwm/6DYJ/+CrVRK ovJ6ttNQLh1uxaIwFq8B7yek8SfrvkL4AVv3Imp0b/jaNVHzN4/5dv/pm1GLDk1JvygW XXnR9cIAsJzEGDNEjvBaqagVPuo+1jLuEuvSA6+gUnuXwPjdNKax8/4AK9GPWr0H0S1R S9NzhN1y0MsDLnorXSQZFmBrXw8ee21oJefgPtPrGpMgQN2fD0aT1/ktzqEzjGaaKySn j0Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303637; x=1704908437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iuIlMixa+qWdIu7SpCSQCDmDPoiwKpmn6qm/naO42AI=; b=o7JbL49qIS6N+XQ4VzlVwqMT0JlEd3PckxHB1aYngSJCzo/NKeiXORTpdQVojNovTd LOBcBtGju1SVDRAJz+6UvFpipQu1XeKUCVOYBrHRfjdlDC0pzOh6sBOt9t90OeAKRRon XzZVUhGtK0fVwat5lh2RUTW5DtH/ZMUmx+wyCLr+7Aen9LxEl7NObJiUGGAFT2uRm13+ +2AI4iUauF8sARdf/KlAIQHQgC81CfPm3+BQrH6XMW2KrxIQDHKGQwkD9zWqDSu7LhHq 2ZPNnkdovAAviJsFT0y5wCqmH5+Z5v+BQ0beOBXoxNOj4q9whQEXDMFBtkI3Z9KA6NMS vunw== X-Gm-Message-State: AOJu0Yz2GDytHlOcVIfmn2VX2rSN0lJJOxAeh0y6v4vAqoaOIYW4jBbt gronhlSQ1K+Xd83jp9nrPD+29ZIn0VsYFBYKnx0EbQgfLVKXVA== X-Google-Smtp-Source: AGHT+IFG7RgRzSWJewNuw7PNEQWgmVz9865RfE5a04Yb0w+skS8lF071qlnK+6/etvYAJu9PUGkVgw== X-Received: by 2002:aa7:85ce:0:b0:6d9:a5e9:528e with SMTP id z14-20020aa785ce000000b006d9a5e9528emr6953694pfn.30.1704303636775; Wed, 03 Jan 2024 09:40:36 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 04/16] target/riscv: move 'mmu' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:01 -0300 Message-ID: <20240103174013.147279-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303906275100001 Content-Type: text/plain; charset="utf-8" Commit 7f0bdfb5bfc ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") already did some of the work by making some cpu_init() functions to explictly enable their own 'mmu' default. The generic CPUs didn't get update by that commit, so they are still relying on the defaults set by the 'mmu' option. But having 'mmu' and 'pmp' being default=3Dtrue will force CPUs that doesn't implement these options to set them to 'false' in their cpu_init(), which isn't ideal. We'll move 'mmu' to riscv_cpu_properties[] without any defaults, i.e. the default will be 'false'. Compensate it by manually setting 'mmu =3D true' to the generic CPUs that requires it. Implement a setter for it to forbid the 'mmu' setting to be changed for vendor CPUs. This will allow the option to exist for all CPUs and, at the same time, protect vendor CPUs from undesired changes: $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,mmu=3Dtrue qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.mmu=3Dtrue: CPU 'sifive-e51' does not allow changing the value of 'mmu' Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e90b70c0a7..9f1407b73f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -419,6 +419,8 @@ static void riscv_max_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; RISCVMXL mlx =3D MXL_RV64; =20 + cpu->cfg.mmu =3D true; + #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif @@ -433,7 +435,11 @@ static void riscv_max_cpu_init(Object *obj) #if defined(TARGET_RISCV64) static void rv64_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ @@ -551,13 +557,18 @@ static void rv64_veyron_v1_cpu_init(Object *obj) =20 static void rv128_base_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + if (qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_report("128-bit RISC-V currently does not work with Multi " "Threaded TCG. Please use: -accel tcg,thread=3Dsingle= "); exit(EXIT_FAILURE); } - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ @@ -569,7 +580,11 @@ static void rv128_base_cpu_init(Object *obj) #else static void rv32_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ @@ -1550,8 +1565,38 @@ static const PropertyInfo prop_pmu_mask =3D { .set =3D prop_pmu_mask_set, }; =20 +static void prop_mmu_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); + + if (cpu->cfg.mmu !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, "mmu", errp); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.mmu =3D value; +} + +static void prop_mmu_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mmu; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_mmu =3D { + .name =3D "mmu", + .get =3D prop_mmu_get, + .set =3D prop_mmu_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), @@ -1572,6 +1617,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 + {.name =3D "mmu", .info =3D &prop_mmu}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303889; cv=none; d=zohomail.com; s=zohoarc; b=L1ekz4iLaxxUgMTSRuwrZTzjslO2lTzs0FviUhDAI+TFozb+XQq0s+brrXWYRGb88VbuAgcYCUkVrh2P5w7HB3JgMAMDU7pNzYcyfqIcUPcW5TvuNKDcokLOl19VOtZGRZfFl1/TLXc4ADjKHWngQpWHzi8ZQ+mvAOfTMYNv91c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303889; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=P47JvB6Aj0fl5W0avy5vyCnxmg8G6WNczQqsL8+H3h8=; b=D1q8GoQ8vZ73HA1Z3zTh2nfI7uNm4le2I33VE+Y8ITDzmj4ZOdXiAk1TMYYcEONaAqH8K0A8jy3ZL24uxK26G4q8hS44nq0d5uQeKcJcVvdzNW/Sn4A9+QT+cR4eb7xTvy9FZJXAs6T8da78tFSZJ0Tv5JDpCTpAajYWWE/dmLY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704303889251920.7145762732978; Wed, 3 Jan 2024 09:44:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5Eg-00044z-HK; Wed, 03 Jan 2024 12:40:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5ET-0002dD-JD for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:46 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5ER-0001cw-Vj for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:45 -0500 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-6da4a923b1bso1434204b3a.2 for ; Wed, 03 Jan 2024 09:40:43 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303640; x=1704908440; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P47JvB6Aj0fl5W0avy5vyCnxmg8G6WNczQqsL8+H3h8=; b=hEc1mPU1/KBHEjewKhZBmnn4AcU/DPC6yp2eR+sLAEEPPYboar+hbtpLjdomESzMMh n0wbgPL6IC4eyb6JgRKvZt5kbrl/DM8QfvU661N8TjNXRUt7V5CmuiK3gm0gKA5UsfFu XvybqEhr2g8nQ50i3IPDIJU6v9wis/MVEYCEvIqT7LZNxRfzl3iWPYGkDyTYqtmSKDGS cACjzXYRNPcpb7NKwQySyDPR8RKKDQ5gz57JwHMmso0HzH0Sbc3MRdDS/oQ8GpXW3qv+ 4I/tNkbVpvcGOufiWA0EuZ8RVAigK/lmZPzSR7qBTlPFWNCDThipoOesw4pcjpL8rKmK xv4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303640; x=1704908440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P47JvB6Aj0fl5W0avy5vyCnxmg8G6WNczQqsL8+H3h8=; b=Pw3zPuiLc2df4NspVUDsHaF8x6ui6AFbRX+B2348JQ4mSiB9Dh6q0CslXvfeWKB+Wn hyQ6OynQUWCgbIdnwc6LO8bxZ14mspOPVSixQyd/wMmGKhxKymUwMQJ8rMepxTO9gU+E x/mccmzE+847L2MZGkg7GDXaZJo27wP+5JbHxiaY0lsezieRZgIlZYjmfqHOefl8/GaG ahxOxwSDKM0HsHrZw3wYzLl4rMJEx568bfoYtgcNCh5qT1bJ25ADC2cJiOCqYGy5X3Q4 h6vd3k/JivIHSEB8imlUrhPnjchyiraV3Wz4k2EP2j+BfDL30bGfYI9Tc6qQb11zdC9P 7PPQ== X-Gm-Message-State: AOJu0YwErHGYKVd5h8OvXHZGRcCiHZzE3XYrVUoOHBs/yT23Or7bVstm 994Kq9sbeM2YfdrcdBFaf5Z8/8kV620heOajQ9arzWZpg5DL+g== X-Google-Smtp-Source: AGHT+IHttDU/YhKaWoA/ylMBkfm9rzgHOYvBgFx5NXAngAqcnieC4a+nU3efuNM69s82WG0q5RvbQg== X-Received: by 2002:a62:5f86:0:b0:6d9:c16b:207c with SMTP id t128-20020a625f86000000b006d9c16b207cmr5616662pfb.10.1704303640157; Wed, 03 Jan 2024 09:40:40 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 05/16] target/riscv: move 'pmp' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:02 -0300 Message-ID: <20240103174013.147279-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303890098100001 Content-Type: text/plain; charset="utf-8" Move 'pmp' to riscv_cpu_properties[], creating a new setter() for it that forbids 'pmp' to be changed in vendor CPUs, like we did with the 'mmu' option. We'll also have to manually set 'pmp =3D true' to generic CPUs that were still relying on the previous default to set it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f1407b73f..01b3b57cee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -420,6 +420,7 @@ static void riscv_max_cpu_init(Object *obj) RISCVMXL mlx =3D MXL_RV64; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; @@ -439,6 +440,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); @@ -568,6 +570,7 @@ static void rv128_base_cpu_init(Object *obj) } =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); @@ -584,6 +587,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); @@ -1596,9 +1600,38 @@ static const PropertyInfo prop_mmu =3D { .set =3D prop_mmu_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), +static void prop_pmp_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); =20 + if (cpu->cfg.pmp !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.pmp =3D value; +} + +static void prop_pmp_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.pmp; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_pmp =3D { + .name =3D "pmp", + .get =3D prop_pmp_get, + .set =3D prop_pmp_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), =20 @@ -1618,6 +1651,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 {.name =3D "mmu", .info =3D &prop_mmu}, + {.name =3D "pmp", .info =3D &prop_pmp}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303677; cv=none; d=zohomail.com; s=zohoarc; b=WGn/1/VxH7TD+OUjMp4VonfZ7ZfMgmZpHjXtQXn9y249WLgRKh2L+UhDJOHJu+/vh0ecC7ffiKlox8zm7If/lg17jSQ1ANxaFGOg4dk6p3VEPkWsJSW+Pu/8fliQX+L6tnLfLVmYmBq1DPIh6/5scVAJLVo2SdQ/jNDiIEEq5yo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303677; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j9FLMG9CAE7ALWgiMWmYvxQJdqWs+YAB7ykqY3X8jZI=; b=RwM/UM/cBYbtk5CIWx3fN7guFBEz+318ncz6ICRnjS2J/lkaTqdda+y1fVyV80PXtObToEioe5+kAFeAjTvCzgX5G0QrXj+2NIr2jp3ICih2tcBTMs4spzT+vBUmwIYVXhwzdl/ufiKgYpUQy162dJTscZ+aNX17qwtnKyq6Kug= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170430367716669.39384382358844; Wed, 3 Jan 2024 09:41:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5Eb-0003X4-TP; Wed, 03 Jan 2024 12:40:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5EX-0002xb-Ly for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:49 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5EU-0001du-A7 for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:40:49 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6d77c6437f0so3546394b3a.2 for ; Wed, 03 Jan 2024 09:40:45 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303643; x=1704908443; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j9FLMG9CAE7ALWgiMWmYvxQJdqWs+YAB7ykqY3X8jZI=; b=L2FfbnCjHvtzteLwF3W7+NHqTSmgmnK4BJZDTs1xfNyKQ1qiTUEu7Q2wTs8sD1jRVO MATmAMxfPb3oyctCZLjxlaj0evXcp1YgdrCKk2Ep/BjAWJy8OlpC/yebB8FJ8WssqJM/ x1vAyQYRrjIrUNr6tKbq9pNm2rr601lP+DJvcA6Mnb+8ZeVvE5MKe5BjawPXCnfqNHAD ITn01yfP+MGg9IIgxseGrwivRztl/yuQ+iqeQdDqRhnnIiyjyUTV7zdPNz35/NiUmQlp GJ27ptBgaCHz3H3HJTi5W5xHmwzYzN5HHXAWoZ1glwd7v6giBP8Rj6qXGQFowIT2SwI6 OimA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303643; x=1704908443; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j9FLMG9CAE7ALWgiMWmYvxQJdqWs+YAB7ykqY3X8jZI=; b=kKpOSEZgKkWKkls+3Hp3x6ZKunT9ZUd60kX8xR44Ln3Cja839DAth5JRJlM0X69+dT 6HQwOWBjVZ6s9/r/RiZlpLuNJ5I1KCxXExjrDBQYRjW74igkkhtLOsYfJcQF/MmQqM5t woJCGZ/KxOIDBQbk6+DoMJNT8H1EJmVmw1E7HL+wqJ+OC/kWQ1NHtATNAy3wCdaE+deu csf0dO3ESY/IsdwuThNbbXj6pEORIzqgPSk9b2k7VMOJb3E9J6areyPXNGg5FmYsctio HUZ6dtcrE2Pj0fK1uQ1lRdInKSqsZI/n+AgeG299dR8emM4/cFn5OptrneP9Xt8xvvvz YcaQ== X-Gm-Message-State: AOJu0YwKq9ZN5wwnE5x1p+c3oiaq9zXsbTzkv84kU5ZfLj2lJuylDbAq wGJIzgXI1nHrbGhCyTgLV3WA+EXtehFVp4aBEyiikfulnawjBw== X-Google-Smtp-Source: AGHT+IE8QOnDt6UdRkFSV9AZ3jaRg2kQd0tRzotNMc9EBuov7bu+83h/mM4Qx2nvG0DmTR6imT69IA== X-Received: by 2002:a05:6a00:13a1:b0:6d9:98ea:e8ad with SMTP id t33-20020a056a0013a100b006d998eae8admr10594521pfg.47.1704303643448; Wed, 03 Jan 2024 09:40:43 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 06/16] target/riscv: rework 'priv_spec' Date: Wed, 3 Jan 2024 14:40:03 -0300 Message-ID: <20240103174013.147279-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303679273100007 Content-Type: text/plain; charset="utf-8" 'priv_spec' and 'vext_spec' are two string options used as a fancy way of setting integers in the CPU state (cpu->env.priv_ver and cpu->env.vext_ver). It requires us to deal with string parsing and to store them in cpu_cfg. We must support these string options, but we don't need to store them. We have a precedence for this kind of arrangement in target/ppc/compat.c, ppc_compat_prop_get|set, getters and setters used for the 'max-cpu-compat' class property of the pseries ppc64 machine. We'll do the same with both 'priv_spec' and 'vext_spec'. For 'priv_spec', the validation from riscv_cpu_validate_priv_spec() will be done by the prop_priv_spec_set() setter, while also preventing it to be changed for vendor CPUs. Add two helpers that converts env->priv_ver back and forth to its string representation. These helpers allow us to get a string and set 'env->priv_ver' and return a string giving the current env->priv_ver value. In other words, make the cpu->cfg.priv_spec string obsolete. Last but not the least, move the reworked 'priv_spec' option to riscv_cpu_properties[]. After all said and done, we don't need to store the 'priv_spec' string in the CPU state, and we're now protecting vendor CPUs from priv_ver changes: $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,priv_spec=3D"v1.12.0" qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.priv_spec=3Dv1= .12.0: CPU 'sifive-e51' does not allow changing the value of 'priv_spec' Current 'priv_spec' val: v1.10.0 $ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 73 +++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 3 ++ target/riscv/cpu_cfg.h | 1 - target/riscv/tcg/tcg-cpu.c | 29 --------------- 4 files changed, 75 insertions(+), 31 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 01b3b57cee..657569d8a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1631,8 +1631,77 @@ static const PropertyInfo prop_pmp =3D { .set =3D prop_pmp_set, }; =20 +static int priv_spec_from_str(const char *priv_spec_str) +{ + int priv_version =3D -1; + + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_10_0_STR)) { + priv_version =3D PRIV_VERSION_1_10_0; + } + + return priv_version; +} + +static const char *priv_spec_to_str(int priv_version) +{ + switch (priv_version) { + case PRIV_VERSION_1_10_0: + return PRIV_VER_1_10_0_STR; + case PRIV_VERSION_1_11_0: + return PRIV_VER_1_11_0_STR; + case PRIV_VERSION_1_12_0: + return PRIV_VER_1_12_0_STR; + default: + return NULL; + } +} + +static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + g_autofree char *value =3D NULL; + int priv_version =3D -1; + + visit_type_str(v, name, &value, errp); + + priv_version =3D priv_spec_from_str(value); + if (priv_version < 0) { + error_setg(errp, "Unsupported privilege spec version '%s'", value); + return; + } + + if (priv_version !=3D cpu->env.priv_ver && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %s\n", name, + object_property_get_str(obj, name, NULL)); + return; + } + + cpu_option_add_user_setting(name, priv_version); + cpu->env.priv_ver =3D priv_version; +} + +static void prop_priv_spec_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + const char *value =3D priv_spec_to_str(cpu->env.priv_ver); + + visit_type_str(v, name, (char **)&value, errp); +} + +static const PropertyInfo prop_priv_spec =3D { + .name =3D "priv_spec", + .get =3D prop_priv_spec_get, + .set =3D prop_priv_spec_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), =20 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), @@ -1653,6 +1722,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "mmu", .info =3D &prop_mmu}, {.name =3D "pmp", .info =3D &prop_pmp}, =20 + {.name =3D "priv_spec", .info =3D &prop_priv_spec}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf69cb9a27..aa3d3372e3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -77,6 +77,9 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) =20 /* Privileged specification version */ +#define PRIV_VER_1_10_0_STR "v1.10.0" +#define PRIV_VER_1_11_0_STR "v1.11.0" +#define PRIV_VER_1_12_0_STR "v1.12.0" enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c67a8731d3..2dba1f0007 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -135,7 +135,6 @@ struct RISCVCPUConfig { bool ext_XVentanaCondOps; =20 uint32_t pmu_mask; - char *priv_spec; char *vext_spec; uint16_t vlen; uint16_t elen; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a09300e908..4d67b72d9e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -175,29 +175,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) } } =20 -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - int priv_version =3D -1; - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - - env->priv_ver =3D priv_version; - } -} - static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { @@ -625,12 +602,6 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Er= ror **errp) CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303647; x=1704908447; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ndaYpmSWzGIFvdIyrDqqU7e6OzktvOjY47Ac1Mpi4+U=; b=kmHdBXceGVuy7SteiFfJUvwmIv/khPsSgQ8/n5wz6AIh3NAOddcYK2txWPWp+dluvk erKSIG/lhFSLXCvMygOSi4bNkFBALvbhN27IUglylQqIPflj/Me7acdV0wJQ952pssC6 H52jEMVCncJx8HQVZOGDK71ANzul5pdOQRUV2DnJrkl4yztezVpgVCP+YSaskBNS+Dwl 0AxPL0QdxMHszkuiXHwueH4KBDoyikDeRBXB0Y8AzQBH4zdniYlKbJZAYVLwNpuy3Mnd MjSG9Uc8tLBNxm59MH0mlct1xwiNpNRLknF2XwyXTEV7DOji3bO835wq3rRjUlseDIqd MdCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303647; x=1704908447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ndaYpmSWzGIFvdIyrDqqU7e6OzktvOjY47Ac1Mpi4+U=; b=YzYGyT2CR1Y+/5AsjWve98gaMbZQ6zPQ/1iiCfZBDoYFLzsib/4VNgvrqnTx0vObqR +AuAio2m7KaEXyNUcoZZS9/XmKvjbDKTuGQVXaAKMpBxxnYVuagiYSxycwU97x6RqNgI 0xxtKZHiVuEAlu7F6f8al5prgmawTDbosuU6pcp0fDv6i43BubWzT9kiW55u2YYmKesV 3g84GkNF+W9A2Yuz7yj2w2pAmia15L+3aMg2LQKGs916NZ2F6DdlEISOQeUYQIIGDYAq ZLfrQEub5l5LeWwJRLj256u7B50P1RN9QUQ70N5OHJ65+EXW1PBzOf+qfeMXhdoqPc9p yuMQ== X-Gm-Message-State: AOJu0YwkPGhXK/EzCPXApX1mcDikY1oP0vk8cmhFUoUwmDpaKNYdD+Kq PtA3pCnu14erqsCdoKaB0Aw3vlEKuS1qVPreAJUjHoa1PofwDQ== X-Google-Smtp-Source: AGHT+IFFWjlQeOIIBgMEZZLSMWNtWuE3ioK0q6ej3luiZr/+INT29yGdOIIUYwMWyzFCmV+sYyAgMw== X-Received: by 2002:aa7:9828:0:b0:6d9:9793:37c6 with SMTP id q8-20020aa79828000000b006d9979337c6mr22662562pfl.8.1704303646718; Wed, 03 Jan 2024 09:40:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 07/16] target/riscv: rework 'vext_spec' Date: Wed, 3 Jan 2024 14:40:04 -0300 Message-ID: <20240103174013.147279-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303984607100001 Content-Type: text/plain; charset="utf-8" The same rework did in 'priv_spec' is done for 'vext_spec'. This time is simpler, since we only accept one value ("v1.0") and we'll always have env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to convert string to 'vext_ver' back and forth like we needed for 'priv_spec'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 35 +++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 - target/riscv/tcg/tcg-cpu.c | 15 --------------- 4 files changed, 34 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 657569d8a6..c39da44f51 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1267,6 +1267,7 @@ static void riscv_cpu_init(Object *obj) =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 typedef struct misa_ext_info { @@ -1701,9 +1702,38 @@ static const PropertyInfo prop_priv_spec =3D { .set =3D prop_priv_spec_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), +static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + g_autofree char *value =3D NULL; =20 + visit_type_str(v, name, &value, errp); + + if (g_strcmp0(value, VEXT_VER_1_00_0_STR) !=3D 0) { + error_setg(errp, "Unsupported vector spec version '%s'", value); + return; + } + + cpu_option_add_user_setting(name, VEXT_VERSION_1_00_0); + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; +} + +static void prop_vext_spec_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const char *value =3D VEXT_VER_1_00_0_STR; + + visit_type_str(v, name, (char **)&value, errp); +} + +static const PropertyInfo prop_vext_spec =3D { + .name =3D "vext_spec", + .get =3D prop_vext_spec_get, + .set =3D prop_vext_spec_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 @@ -1723,6 +1753,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmp", .info =3D &prop_pmp}, =20 {.name =3D "priv_spec", .info =3D &prop_priv_spec}, + {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa3d3372e3..f1715d9d31 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,6 +89,7 @@ enum { }; =20 #define VEXT_VERSION_1_00_0 0x00010000 +#define VEXT_VER_1_00_0_STR "v1.0" =20 enum { TRANSLATE_SUCCESS, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2dba1f0007..7112af6c4c 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -135,7 +135,6 @@ struct RISCVCPUConfig { bool ext_XVentanaCondOps; =20 uint32_t pmu_mask; - char *vext_spec; uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4d67b72d9e..6501c29d8e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -201,21 +201,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, "in the range [8, 64]"); return; } - - if (cfg->vext_spec) { - if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - env->vext_ver =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, "Unsupported vector spec version '%s'", - cfg->vext_spec); - return; - } - } else if (env->vext_ver =3D=3D 0) { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - - env->vext_ver =3D VEXT_VERSION_1_00_0; - } } =20 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303812; cv=none; d=zohomail.com; s=zohoarc; b=nSzOWuZN8V1p0YJn/24hCqTAK84X0pEahVPEqeSdmHzNE6xrnIMvEC3f+NF1VPKkS2dtIcsBKEkmU4xGP2m/eR88xOVcNOcTItVdTliYAlcqET49P+uzLGUOPiNyysnTHid0t8KMlHEM/yQjziNJS25k9KzeOi/FABdqm/A9qEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303812; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Lf45moVsB1V70aKXjn6Z7X3nShbqPvle7BNNm9DCtHg=; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303650; x=1704908450; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lf45moVsB1V70aKXjn6Z7X3nShbqPvle7BNNm9DCtHg=; b=o7uRFLJuwmA6xPussQvKXvl5DoCJ8zqZkh3E5hcYVdzFYv2NMR6ktR/8orucvlj2yU Curs8ouC/Gdi/2BVED5vrX7AioFSCEJgCmZwGR7YKGygs8qCBWKswihILTZQ5E4sBiIL V+DCSst6dUQbl7V4Qo2alNTJ15Xbt9RQCWH7Vh/r7FYfw/60pwHRZ0+tVypB33pGhtNW 5uH9N96KIbVXx6wEFbP39JhMDiJul7BFoPGoeeRCFehmvv7SN8Ph9GyrhsyLUKm6F7zP AX6VJpLk/XSJWQcJauSjBoDnaLEEW5Zj7cGNveHidmVN21ijaRDZHg1YdgeegzXgxGw5 f25Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303650; x=1704908450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lf45moVsB1V70aKXjn6Z7X3nShbqPvle7BNNm9DCtHg=; b=o0j7DhH8E0Dg7+1QD0AMFo740vzfXLhy6Iw3u6+/ZdhK2iSFoSIG7U0P73Crfysgrd Hhavhs+LlShJ+ru4SvM6OdzXOrXq2xyTigfwDyhfkAxxhwIcN5sYGOyXZMzEHQaX6W1C isqNRd4O7nrZuf+TE/J/R7OLO5VgNNUymnH0hUAS+dLZChUBxpHByMFDdwV1ThIf0G25 DXFfSPEvCQFSQvNFLxqY5Rqpe6y1Gm7T3M1EGE5EX/mBa3Vfxl4iwhhp+F/52zPgMN4p lDuszlxwajpbP333hRveE4oHEmnzK9eSIRYAy+68C9nDSdVGAgGsOBjHm5OVxl/rHw/f F00Q== X-Gm-Message-State: AOJu0Yz89OXR2nTABBFtqQhuf6PpviCgYrTA2ScuwVn3xIo1V9mzNffj qhHcX9K/nIKKjIiQuyZkOllBuCFsblnisCAUUeV0PKdJsjI6BA== X-Google-Smtp-Source: AGHT+IFCMVDzevNCf3ERFrj0IupnV83wOk+utnq2Tr9ry5eB+7TTwLTkwdsUZ9kyFt8RabE1QaLYJg== X-Received: by 2002:a05:6a00:26e3:b0:6d9:9edd:60a0 with SMTP id p35-20020a056a0026e300b006d99edd60a0mr6252093pfw.46.1704303649915; Wed, 03 Jan 2024 09:40:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:05 -0300 Message-ID: <20240103174013.147279-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303813779100001 Content-Type: text/plain; charset="utf-8" Turning 'vlen' into a class property will allow its default value to be overwritten by cpu_init() later on, solving the issue we have now where CPU specific settings are getting overwritten by the default. Common validation bits are moved from riscv_cpu_validate_v() to prop_vlen_set() to be shared with KVM. And, as done with every option we migrated to riscv_cpu_properties[], vendor CPUs can't have their 'vlen' value changed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++++++++++- target/riscv/tcg/tcg-cpu.c | 5 ----- 2 files changed, 44 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c39da44f51..557874a017 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,6 +29,7 @@ #include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" +#include "hw/core/qdev-prop-internal.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" @@ -1267,6 +1268,7 @@ static void riscv_cpu_init(Object *obj) =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); + cpu->cfg.vlen =3D 128; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1733,8 +1735,47 @@ static const PropertyInfo prop_vext_spec =3D { .set =3D prop_vext_spec_set, }; =20 +static void prop_vlen_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (!is_power_of_2(value)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + if (value !=3D cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.vlen); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.vlen =3D value; +} + +static void prop_vlen_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.vlen; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_vlen =3D { + .name =3D "vlen", + .get =3D prop_vlen_get, + .set =3D prop_vlen_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), @@ -1755,6 +1796,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 + {.name =3D "vlen", .info =3D &prop_vlen}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6501c29d8e..8ec858e096 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -178,11 +178,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303653; x=1704908453; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=spt/SNkoSMqjDanR+c9fz/f8kAKZjlIFuVgb8nW7NcE=; b=N8fLxOvOk93zcLuNuyds93bVN0mKp5SaT8ZRIOywFwhiJwpqAiGYtSb2vqOmGY5kJv 8q7moKMbTHfQnI0dwf++DEPe6cJ2ScPba5cmTse/EFr3KJVNSazst2FOzNjRRVVCTQ0/ llJAysDlBEvSNq2NDaURzsOo7drQjYau+clHZxlOLrTJn2Wz7QvJAPinZejzO4NGuSyY rb+zkN24VbGfU5x+zHcg/pt4wLSPzvkYr5NlXrvLQLbIwmBRvW0aGpvZok7zd5TfSCA8 JK9QkcWEuhwQDIezpbUow/voaXJmPThaLsvJarW0GUZEhVUH9v92RB0tItOPDhQp5TKo vdCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303653; x=1704908453; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=spt/SNkoSMqjDanR+c9fz/f8kAKZjlIFuVgb8nW7NcE=; b=q3rnO5UvbuNuBtatdmgt8k7uaQ2Gl1NGIeSwnh/6qqhHNMVCt454e5TyqDcbbsR6CD a/SC5cn6Wy1J6x+qq+JwWLKtcQ7Sppg2U2+yKf0Gyacu2rJLuoekGTQrKMqg8IgPM8i6 xTGV2qieSBJL2uLSN+vtcdpKaiiU7QvU6SuJkF+y/sKgR0BvYSldPVjiE7wvGNsygBlD WSGXV1n3qzGQf9A52maseBRXxoPxjinPMSi7fXFma14LzvmvmoVZmwnACIZ+EHSwIzTj RZDHuGD/ICdNajM8wNwICHMU+0GjO5wif3LRT4AMg3M/WsIVUG1VxMhL9Gfg2dUfWq1k zbLA== X-Gm-Message-State: AOJu0Ywkajtwzec/uPiIpiR17nKp9jhSc2i290G14jSyJodMpvG3RqSe Cd8gUpz48ZpJUQJUjkZTaqAJ4KiP+BlyESSAED0KQMP578lIPg== X-Google-Smtp-Source: AGHT+IHa5Pqj9ZX8Qn2bmR8llKZvoFKb2DKqLq4K8KkltcKCtzLc+zM6SgWz3hVQGNw+sv2qqQoUhw== X-Received: by 2002:aa7:860d:0:b0:6d9:ac79:cbb4 with SMTP id p13-20020aa7860d000000b006d9ac79cbb4mr7080268pfn.24.1704303653183; Wed, 03 Jan 2024 09:40:53 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 09/16] target/riscv: move 'elen' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:06 -0300 Message-ID: <20240103174013.147279-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704304167533100001 Content-Type: text/plain; charset="utf-8" Do the same thing we did with 'vlen' in the previous patch with 'elen'. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 44 ++++++++++++++++++++++++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 5 ----- 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 557874a017..da432e4c1e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1269,6 +1269,7 @@ static void riscv_cpu_init(Object *obj) /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); cpu->cfg.vlen =3D 128; + cpu->cfg.elen =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1775,9 +1776,47 @@ static const PropertyInfo prop_vlen =3D { .set =3D prop_vlen_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), +static void prop_elen_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (!is_power_of_2(value)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + + if (value !=3D cpu->cfg.elen && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.elen); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.elen =3D value; +} =20 +static void prop_elen_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.elen; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_elen =3D { + .name =3D "elen", + .get =3D prop_elen_get, + .set =3D prop_elen_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 @@ -1797,6 +1836,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 {.name =3D "vlen", .info =3D &prop_vlen}, + {.name =3D "elen", .info =3D &prop_elen}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8ec858e096..84064ef7e0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -185,11 +185,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, return; } =20 - if (!is_power_of_2(cfg->elen)) { - error_setg(errp, "Vector extension ELEN must be power of 2"); - return; - } - if (cfg->elen > 64 || cfg->elen < 8) { error_setg(errp, "Vector extension implementation only supports ELEN " --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303774; cv=none; d=zohomail.com; s=zohoarc; b=GxqcH9Xg4D1v0CYE/tDZrfxoEymJvARz/A4uRMpxiU+yvCE4XOJtaUxe3Z/6DCWdpkItxGhAWhToebb52F14VwiI8dDgffI2KDF4QOGWDdAya5A2T17ee5/BDA196VpPhewtx9Kt9PdcwG/uJ2GUg7MhqkxhV2LzZn7DXjqrmmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303774; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303656; x=1704908456; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KCqEJqvOs1M1K8ABiO2IzEPvdUeqoMhjDMz6ZppTteE=; b=F0IoSy0QKagwSgvCZodyjmi+FcO1cEiRoguy93mG6mGK/7nO5AV1/P0pmDnlg8Qp94 a5WHo7+eh2RtmSdZP3h6RtU+eTB/83qUg1SbI1Z3o12T3U3LU6TsFYj7gM2QhJ/jMZXv XTC1t2dqtFIC48M+ILK0dydyLlIRc0XR/bGwI0JZq5xe+FAD5mD+DsNOYuICOw1PgyyK vkowO8Ohtnt9QyU4kpuf4aXAhgmMKYvTsGCPAMw1yRXZe+1C1Z9xwAs81kWAG+Fc8EdZ TVYm5tG+DxT2Fo+s6864aaV6X4eJ0AkCEUiP57P30LMgxYtKdrIJoZwyAxAKxBkhfpOW +v9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303656; x=1704908456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KCqEJqvOs1M1K8ABiO2IzEPvdUeqoMhjDMz6ZppTteE=; b=NdUYkUkbzHIcUO2PkJU/yUUP0Mypr8trcs2PgOJrR1TXJAQ3r/v5VIX7H3VjDDDhju 5gwdmXEIQ2KCcgkZqBrssb34KgWziKD6dp9IChu+UQFT/MBQeQEcxEYSn+XrccZjiUBB j2MDyvctLEqEaU08Gg9zJ3Q9K+TwJPN450a5dPpvp/4lC/ErrqkU7RKV4gzIq+qDwofp desHnvIo9YTKr/G2LhnLHtL8+tdld3tgXUub06aFK0eSX8lNFoTVUWYQFPV8+cI6pjRt xuRgk7k2Ln3IOj6kDyTbFyppHN6Sp8qvJfDSD/P1765Np5cv50riQiNugbWrh9aTAyM+ DGHg== X-Gm-Message-State: AOJu0Yyw1VmUoqb2aD3+uoWdhMGvhzLkKq2B+ZVSbcSzZSpNenWAhS8T YmhEK4eqmgdSZypZ2GXSOtCI92VKOTJ7aFyFC/YQX5huVNwokg== X-Google-Smtp-Source: AGHT+IF0i9Hg4MIKZQYKXuRYlsP3ssINh5wY3o67egI5uceAB4U8Bw6B5H4jpX04bp1O7fCDVJ6dMg== X-Received: by 2002:a05:6a20:8f14:b0:199:4e1:fec2 with SMTP id b20-20020a056a208f1400b0019904e1fec2mr36349pzk.50.1704303656455; Wed, 03 Jan 2024 09:40:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 10/16] target/riscv: create finalize_features() for KVM Date: Wed, 3 Jan 2024 14:40:07 -0300 Message-ID: <20240103174013.147279-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303775641100001 Content-Type: text/plain; charset="utf-8" To turn cbom_blocksize and cboz_blocksize into class properties we need KVM specific changes. KVM is creating its own version of these options with a customized setter() that prevents users from picking an invalid value during init() time. This comes at the cost of duplicating each option that KVM supports. This will keep happening for each new shared option KVM implements in the future. We can avoid that by using the same property TCG uses and adding specific KVM handling during finalize() time, like TCG already does with riscv_tcg_cpu_finalize_features(). To do that, the common CPU property offers a way of knowing if an option was user set or not, sparing us from doing unneeded syscalls. riscv_kvm_cpu_finalize_features() is then created using the same KVMScratch CPU we already use during init() time, since finalize() time is still too early to use the official KVM CPU for it. cbom_blocksize and cboz_blocksize are then handled during finalize() in the same way they're handled by their KVM specific setter. With this change we can proceed with the blocksize changes in the common code without breaking the KVM driver. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 16 +++++++--- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 59 ++++++++++++++++++++++++++++++++++++ target/riscv/kvm/kvm_riscv.h | 1 + 4 files changed, 72 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da432e4c1e..92b4881e9c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -63,6 +63,11 @@ static void cpu_option_add_user_setting(const char *optn= ame, uint32_t value) GUINT_TO_POINTER(value)); } =20 +bool riscv_cpu_option_set(const char *optname) +{ + return g_hash_table_contains(general_user_opts, optname); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1056,17 +1061,18 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) { Error *local_err =3D NULL; =20 - /* - * KVM accel does not have a specialized finalize() - * callback because its extensions are validated - * in the get()/set() callbacks of each property. - */ if (tcg_enabled()) { riscv_tcg_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } + } else if (kvm_enabled()) { + riscv_kvm_cpu_finalize_features(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f1715d9d31..484c32e607 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -494,6 +494,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +bool riscv_cpu_option_set(const char *optname); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 62a1e51f0a..70fb075846 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1490,6 +1490,65 @@ static void kvm_cpu_instance_init(CPUState *cs) } } =20 +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + KVMScratchCPU kvmcpu; + struct kvm_one_reg reg; + uint64_t val; + int ret; + + /* short-circuit without spinning the scratch CPU */ + if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz) { + return; + } + + if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { + error_setg(errp, "Unable to create scratch KVM cpu"); + return; + } + + if (cpu->cfg.ext_zicbom && + riscv_cpu_option_set(kvm_cbom_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cbom_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cbom_blocksize !=3D val) { + error_setg(errp, "Unable to set cbom_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + if (cpu->cfg.ext_zicboz && + riscv_cpu_option_set(kvm_cboz_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cboz_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cboz_blocksize !=3D val) { + error_setg(errp, "Unable to set cboz_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + kvm_riscv_destroy_scratch_vcpu(&kvmcpu); +} + static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 8329cfab82..4bd98fddc7 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -27,5 +27,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state); +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); =20 #endif --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303659; x=1704908459; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gcJgCanuDO16+bp0jo2nfKBsMMHLb9tW9PJJIRWNfao=; b=ojBkH9gQWg7UKoyhTNyPsmsmsiRe5ue/MZimE8RQTPfViag4D7klUk36FlQb7Ln9G8 ksqp5NZ8WEZUYowwij0GEvEAGI3NBZQylkKNeDrGTPWNSVwHqzDx2TbxbjNFl5qv1r7V IX7KVsLGX70OsPxi4i32qydcY2V9IPG/Fkl0DzPUGkzRfiKrr2wlWJFeVcVLwlNl9GYI hG4p3ux1eJM0NVxAHFgwm6iSA6ZvhIOJsDcHurUL3l4W+Sg3NQdAqNRPXvshbzr+Im1E lZ7R0mZhHHry0VA/DJ1cx1DPUpu9743RR9wos0kDfRnI7Faf6YzOPUKoArlxbocUDCBu MAww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303659; x=1704908459; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gcJgCanuDO16+bp0jo2nfKBsMMHLb9tW9PJJIRWNfao=; b=Zi3wAsR59YW948jhn6g5/cQAbu3/vCb5QId1prbJedV1XJEZITM0Gly3X51KX/NNkh Lxm6y6qkM7EKYmktwRJwuUtwhAfw+IpLZnsTUpeHyQjjmKL95AiRE1JiH4h8kzGpmuSu BaW2VzeFEs3dM0Y0ZZQuWTdXKuvqg13iNbPqYDLvVid/8JUtJBHwOzytofo1P7Ppgu0b PuaifqV6W/MrF2HH8s5JSIPRJ69bXszFyQa7ENNc/Ap5r53pmLbr+0EljNe3gozaOUr0 pU7PmYvW/MgcZ86TXO72ARcEwLKtr0Gp8UAkTS6Wk31b1ZhRjE1I2JJwgKlX/6XUvHOO aw4A== X-Gm-Message-State: AOJu0Yyg0dyzbcHQ2nw5c4hGpY4s2N/L1pxK6rBnPxV3sWYPv6BLaQVD RqjC4jCsNCmNY+lGqiRU8JUE4O5qso0cK4G8DZaCDIdKMgfpTw== X-Google-Smtp-Source: AGHT+IHxG4/01DVaNa+Fx0kHWOV0SLYGHuFvCYtsPrI55qmALpoyvk1c+Ui1JGIUwsBpZM2Y7PZt/A== X-Received: by 2002:a05:6a21:7989:b0:195:2f17:9884 with SMTP id bh9-20020a056a21798900b001952f179884mr25496031pzc.20.1704303659610; Wed, 03 Jan 2024 09:40:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 11/16] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:08 -0300 Message-ID: <20240103174013.147279-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303803767100001 Content-Type: text/plain; charset="utf-8" After adding a KVM finalize() implementation, turn cbom_blocksize into a class property. Follow the same design we used with 'vlen' and 'elen'. The duplicated 'cbom_blocksize' KVM property can be removed from kvm_riscv_add_cpu_user_properties(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 4 ---- 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 92b4881e9c..b510cb94fc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1276,6 +1276,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); cpu->cfg.vlen =3D 128; cpu->cfg.elen =3D 64; + cpu->cfg.cbom_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1822,8 +1823,42 @@ static const PropertyInfo prop_elen =3D { .set =3D prop_elen_set, }; =20 +static void prop_cbom_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (value !=3D cpu->cfg.cbom_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cbom_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cbom_blocksize =3D value; +} + +static void prop_cbom_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cbom_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cbom_blksize =3D { + .name =3D "cbom_blocksize", + .get =3D prop_cbom_blksize_get, + .set =3D prop_cbom_blksize_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), @@ -1844,6 +1879,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "vlen", .info =3D &prop_vlen}, {.name =3D "elen", .info =3D &prop_elen}, =20 + {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 70fb075846..1866b56913 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -484,10 +484,6 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) NULL, multi_cfg); } =20 - object_property_add(cpu_obj, "cbom_blocksize", "uint16", - NULL, kvm_cpu_set_cbomz_blksize, - NULL, &kvm_cbom_blocksize); - object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704304153; cv=none; d=zohomail.com; s=zohoarc; b=ZbRnwT0zkzD4fDL2iSmF8UmUOdcIMxV4JY8KOCBLRhbCUoUF/8ceqrgMxHpKI71nhBaTUuNlQliXI3XNdGBnVCODPhEPMrnyoS88riKGXEcBHwPmtW4e3Mk95t+Uj0l0piIa5b/vRHGqpXAvklH2dwwBQZD6AZR83mYmKM0/C7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704304153; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=V5RXRQLi/lm91YvCTdeSrbK4N/hfbqHvfE18ltsqAwQ=; b=Q5HfnnxW6ZFjV8H7gjFXOQ12fHWw9L9vEYlBCgU/K8n+BhY+RL9wkO5ophtjkuykfwVFfJWKxqG1QxTyvwc+YG6100Tg6e6gNmonUmFSvTvfRNI1XLXP+TH9yzpiG5xcqhs+NC47zdbJ2w9i0ASfjZA5oua1hSFMYdm62O5OzkY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704304153655285.6698906050268; Wed, 3 Jan 2024 09:49:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5Ex-0005fq-Lf; Wed, 03 Jan 2024 12:41:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5Ep-0005Eg-5Z for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:41:07 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5En-0001lx-51 for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:41:06 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6daa89a6452so976556b3a.2 for ; Wed, 03 Jan 2024 09:41:04 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:41:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303663; x=1704908463; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V5RXRQLi/lm91YvCTdeSrbK4N/hfbqHvfE18ltsqAwQ=; b=IZk3kBLl2KInx101BfcsGctCMDURfBXY9cFmuccbKtnowu8ERyg9291Oi7D6UG08WG jmXZaQ3NGnQDz/YYSoNfMibqUyR1S8B1hZeuw5qBqVB1sByYrhxWaXxK8K39R1ECOTxa 0IZL3jg3DQem8OVnrdXTWm2lFCilcdPjuVQ3a1wGUc/qXRU8+FOsHBy+e4zIZ1qZR2Mi LH5AT4F6kwOCYhpUeOYHiIbUHVRpBbAE8Fc9kNIBIk2to/WBKYgXH/9iVJXwhi0L9tRq nuf5HD4vA190+xDJ0yYTUZtkVhymnaKyn0QzF/8vG9WrNvSvBdI+CXdicW2KrBsx6fUe YnNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303663; x=1704908463; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V5RXRQLi/lm91YvCTdeSrbK4N/hfbqHvfE18ltsqAwQ=; b=rRlN2SmfTt4fonbXyS+MCMP8VBLOOwmMbdrNLa4f7ziKs9SlDpSfwUasm+zVvoj3Iu Bhq5XwGPkOYhvz6TJu7emgCVhP4PpkGGcVU6fZHVYkgZ/Rb8tbaj5e/Kaxmo03WDityU Bm1HCurVi8KsrIsAk8NUjaHQBKATQpE3nfmwfw5f50CwwgGMH4FRYq2gTczwuXXuSd3K PE3PUKAj+tZbiEbCTCSXT11hig5lFykIQcK/Lc81AC16IpF7VUz4tiRrpZD6nspHENQD uxQy5iAQZU5CWRGTnXW7/M2Xyo8FH6jjClqTl7SGMh1AQ4Pz0JZkPDFMuZnbIjdOhDYX NT0g== X-Gm-Message-State: AOJu0Yyb0LXfy5tWU2X20wwNugJl9YJXYxAFDvbmwH6SIbi2BCWEDTtw hxqsr6i7EyksWbtAWe0SFeblx9OPbdmTYHf70IiFcCOmoUm7sg== X-Google-Smtp-Source: AGHT+IGl+lekf2bXh2hQlZD8GHOjHYUFYWjizMWCbFXGimDq84MthYVfhUdMHGaUhO3jaPg8nk1T3g== X-Received: by 2002:a05:6a00:4b11:b0:6d9:eb5c:8ccc with SMTP id kq17-20020a056a004b1100b006d9eb5c8cccmr7747390pfb.34.1704303662892; Wed, 03 Jan 2024 09:41:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 12/16] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:09 -0300 Message-ID: <20240103174013.147279-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704304155491100005 Content-Type: text/plain; charset="utf-8" Do the same we did with 'cbom_blocksize' in the previous patch. Remove the now unused kvm_cpu_set_cbomz_blksize() setter. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 28 ---------------------------- 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b510cb94fc..1e35b73e40 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1277,6 +1277,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.vlen =3D 128; cpu->cfg.elen =3D 64; cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 @@ -1858,8 +1859,42 @@ static const PropertyInfo prop_cbom_blksize =3D { .set =3D prop_cbom_blksize_set, }; =20 +static void prop_cboz_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (value !=3D cpu->cfg.cboz_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cboz_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cboz_blocksize =3D value; +} + +static void prop_cboz_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cboz_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cboz_blksize =3D { + .name =3D "cboz_blocksize", + .get =3D prop_cboz_blksize_get, + .set =3D prop_cboz_blksize_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), }; @@ -1880,6 +1915,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "elen", .info =3D &prop_elen}, =20 {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize}, + {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 1866b56913..137a8ab2bb 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -343,30 +343,6 @@ static KVMCPUConfig kvm_cboz_blocksize =3D { .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 -static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - KVMCPUConfig *cbomz_cfg =3D opaque; - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint16_t value, *host_val; - - if (!visit_type_uint16(v, name, &value, errp)) { - return; - } - - host_val =3D kvmconfig_get_cfg_addr(cpu, cbomz_cfg); - - if (value !=3D *host_val) { - error_report("Unable to set %s to a different value than " - "the host (%u)", - cbomz_cfg->name, *host_val); - exit(EXIT_FAILURE); - } - - cbomz_cfg->user_set =3D true; -} - static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { CPURISCVState *env =3D &cpu->env; @@ -484,10 +460,6 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) NULL, multi_cfg); } =20 - object_property_add(cpu_obj, "cboz_blocksize", "uint16", - NULL, kvm_cpu_set_cbomz_blksize, - NULL, &kvm_cboz_blocksize); - riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_e= xts); --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303953; cv=none; d=zohomail.com; s=zohoarc; b=MqO1Spl8xdVNHtOumWvhkaS1RgcALHpHcPTZtO5V0I0gAkTZsXX/it5MYlH0GPO7qd13SyQxpxUJga4reRgIzUQkR2+HkRGwB5b5N0wAieyNK9ML7hdZydYi1kgXOualqFMCzJwZxTZelMmrolOmSsqJ+saWSX2vyTNW3c1N0dQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303953; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=56T0F2BPs0Wr6zApRAMz+ioprbzwkEkciuAtikBAF/0=; b=DX7icxDJ9i110Dx6X2GBtCliCKm86Jv+7nv/MeVvcFmdx0vGqS8kL6dXq3EAENBN7oIWoe8h7DDBDzQ9mQI9Q5CQoTR94pnNjBCmpc5gqKkVV+LN9xLrv0KjBo/SjTNJIXiE260kpXOhXRxCUxOGdW5TWAymOCREpoO+r07cIwg= ARC-Authentication-Results: i=1; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:41:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303666; x=1704908466; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=56T0F2BPs0Wr6zApRAMz+ioprbzwkEkciuAtikBAF/0=; b=TgoGeM4mVrPE02MOdsFeVnvhnFlvx3/CU6X+FI2IiysqCo94z8g9quivNcxxbQiNEZ hK9Cs0S0sHzc6gU0/SO2NkosF6+gPYp91f8o2ugxw3A+vlOZH5ktg8/9r4aWck8C8EFV XW0b9pXj4VFhSUswuDYi9a5ePD63K59EC+e8wvKwtnhI8a1HPc2EdK8skELwE4Gs88w6 XYKoDjmQLoY7+CC/zD9u26S7RgFodNoMYxbHlQ0i29b1+RvV+LIejuD0/el18Bs7srlR A0FgglwL88nPMuldyr40KMNCR1ma1tFhNNnIPR3Isy1WZ3jOdaD+C6f7bpuJQyY+6xG2 wcUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303666; x=1704908466; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=56T0F2BPs0Wr6zApRAMz+ioprbzwkEkciuAtikBAF/0=; b=QQmlIWSkjnnYCz7u7nJd4TBEijqys6YvlvUa+pkWVA66TC8sECzKSRwgmHsraoH2sH UMUPSxUsoiLHMx7X/CXZUc8w2O8MquIyNAY5VhhGJjjhtZPtqTdTaA3S68g2OrH9LaFY d1fWWPqT2tdPV5ccbYLLUQAu9FfsteLhatxMudBe1MmaSMCVThta/hd/kE7r/SVYiI7i FQS6gpBplZ0Q+j/AhzmyABVYeFgZjo2iZ81MjM0S7eCoydw9yLh0mJOw9C2vqBtytyxt Mf9DXJ2A9FGKaFB0s1k163aX1En/1UWvTqXvCxrMI8IekRNjmKPkqKWd3kAnCZtj3Xrp JPYw== X-Gm-Message-State: AOJu0YwySCrlwit4b14GOZP+CueLiqPO86iCiQV34h/YxSMLj6eSfir8 Fom/WkWCsVSuO1QyrTVIzQGLyBqpKURJ6Q+RuKD01sGzC1JsYw== X-Google-Smtp-Source: AGHT+IHqvESecQYYKGdl26/ISgcPLgAT68BHBw7XWX9E4seRiTzEPf+jaBJ2TQ4rWyqrRCPBn4vfBA== X-Received: by 2002:a05:6a20:9717:b0:196:e00:29f8 with SMTP id hr23-20020a056a20971700b001960e0029f8mr5824163pzc.32.1704303666036; Wed, 03 Jan 2024 09:41:06 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 13/16] target/riscv: remove riscv_cpu_options[] Date: Wed, 3 Jan 2024 14:40:10 -0300 Message-ID: <20240103174013.147279-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303954432100001 Content-Type: text/plain; charset="utf-8" The array is empty and can be removed. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 ----- target/riscv/cpu.h | 1 - target/riscv/kvm/kvm-cpu.c | 9 --------- target/riscv/tcg/tcg-cpu.c | 4 ---- 4 files changed, 19 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e35b73e40..0d0197a8ef 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1894,11 +1894,6 @@ static const PropertyInfo prop_cboz_blksize =3D { .set =3D prop_cboz_blksize_set, }; =20 -Property riscv_cpu_options[] =3D { - - DEFINE_PROP_END_OF_LIST(), -}; - static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 484c32e607..59e23708d1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -773,7 +773,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_extension= s[]; extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; -extern Property riscv_cpu_options[]; =20 typedef struct isa_ext_data { const char *name; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 137a8ab2bb..5800abc9c6 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1443,19 +1443,10 @@ void kvm_riscv_aia_create(MachineState *machine, ui= nt64_t group_shift, static void kvm_cpu_instance_init(CPUState *cs) { Object *obj =3D OBJECT(RISCV_CPU(cs)); - DeviceState *dev =3D DEVICE(obj); =20 riscv_init_kvm_registers(obj); =20 kvm_riscv_add_cpu_user_properties(obj); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - /* Check if we have a specific KVM handler for the option */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } } =20 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 84064ef7e0..d3eeedc758 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -889,10 +889,6 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); =20 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - qdev_property_add_static(DEVICE(obj), prop); - } } =20 /* --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1704303969; cv=none; d=zohomail.com; s=zohoarc; b=QTWBU/dATVzHe/O4RwOIjwFCcP8vM0i34KGF/kXOp33Lx9uA2c9Gw06Oxeljvof4DnBhGJ/HZfQJ+7ZLhKCKHk4+awDt7I+Tc8ypatVpOJUV92uSXJtd6zf/TPW9v0a6aPRotCZHAfk9APFg17KEnZKIX578YuE81FP7QqZyRtw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1704303969; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oFdaFzrh3PlOhs4z4Tfhlmxx+edYQsfPinw4wO3JTV0=; b=lUpu47d3CcGpAQX/cEzkjEZh2juScdSBdPLtmahjs+azuh3UitbzXfHXnjniqy6NyRVhzzG+yS/dQCDhemRIWorFvWg4khrZZPnkuh/h8KXh8713km9mxzFjeSSlTd6QQ0jrguyPczz8x4CmyFarDYHET5P7ZkjWN6t2c6QEZUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1704303969602228.09094163915597; Wed, 3 Jan 2024 09:46:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rL5F4-0006C2-Dg; Wed, 03 Jan 2024 12:41:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rL5F1-0005wE-Ju for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:41:19 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rL5Ew-0001oO-Ss for qemu-devel@nongnu.org; Wed, 03 Jan 2024 12:41:18 -0500 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-5ce07cf1e5dso2643961a12.2 for ; Wed, 03 Jan 2024 09:41:12 -0800 (PST) Received: from grind.. ([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:41:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303669; x=1704908469; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oFdaFzrh3PlOhs4z4Tfhlmxx+edYQsfPinw4wO3JTV0=; b=nx0FBMNuv7dA42UntI0tuyDvsWJOIUA+hCsgDdvFta8LoccnPK0MFFpNhKcLi+jS0i SixkhETsWa05OIOnMUh2O6ejmfx2024uuM4syPfypdKVSls7BM+45DSuoH4BDwh5hIFF JEZdnPxfgG2MLCP1tuNteY7rgSH8hsOrENtWBN8KrzP3+rINxGgsueyQrkn1xk36nghh rFtDh3XZj9dX2/pGgXRIvxe9ak9eQJGu9ihE7a7NXNikOGCc77Mp6dfnB+ctIgoO6WW0 uYzeNRDDwCwDnbWl5VmR8IVURXmgjPv0qjh/uSxCvruQrDvT59eQ4xCjX5+W984LbToL RdDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303669; x=1704908469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oFdaFzrh3PlOhs4z4Tfhlmxx+edYQsfPinw4wO3JTV0=; b=MVwnrF8RHroM1urYn5iluam3Tt8TRQwXnrIOa5EpnJwUXs4/riLFvtwR4j0I2y9pYW 0m+kRm4WYxM4WwBLaB+LhlaxY29oW3K8B5PsP8IJXrDQQEPXzFydJz6/JjwS49DvJYvT F1n+APyhOIdAJM9TgRTAwfejgKHp27XCwze4XdzjZFyJw7mOhl4/MSbOfFY7cNQA1Kk3 /f7RqLUwctp4L9Bb5cDePrq1eh0Zy1L1gmDu9TANjWw0gRnMOUMo9tg8uX10PQWzm5/8 RH6b1YT7713pkTMYimPPAipuSOuYJpH6tEKJVZ0iPNO9eTh9VTkUIr9xI4AwO/uPMaZm MEQw== X-Gm-Message-State: AOJu0YxLKYbc7Ew/YdWugjBjztZ6tqhp2Fg3+sknDQC4yCbBdMytfb7E +01SZP9N1ml+z4i5uOnoA1V7jQH3iMddLpB+Ezfo8VR7BOXZYQ== X-Google-Smtp-Source: AGHT+IHv9aw9HVjv2cvx1jsKRXWsyoa8LBJLeZ187UzeGTNpgxCyZzstcY2zUOiMaYAGyv6IMF1JTQ== X-Received: by 2002:a05:6a20:9686:b0:196:106d:dd06 with SMTP id hp6-20020a056a20968600b00196106ddd06mr5867363pzc.16.1704303669245; Wed, 03 Jan 2024 09:41:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 14/16] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:11 -0300 Message-ID: <20240103174013.147279-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303970489100001 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 69 +++++++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0d0197a8ef..2fe282d0af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1894,6 +1894,41 @@ static const PropertyInfo prop_cboz_blksize =3D { .set =3D prop_cboz_blksize_set, }; =20 +static void prop_mvendorid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint32_t prev_val =3D cpu->cfg.mvendorid; + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mvendorid (0x%x)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mvendorid =3D value; +} + +static void prop_mvendorid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint32_t value =3D RISCV_CPU(obj)->cfg.mvendorid; + + visit_type_uint32(v, name, &value, errp); +} + +static const PropertyInfo prop_mvendorid =3D { + .name =3D "mvendorid", + .get =3D prop_mvendorid_get, + .set =3D prop_mvendorid_set, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 @@ -1912,6 +1947,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize}, {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize}, =20 + {.name =3D "mvendorid", .info =3D &prop_mvendorid}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif @@ -1976,35 +2013,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t prev_val =3D cpu->cfg.mvendorid; - uint32_t value; - - if (!visit_type_uint32(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s mvendorid (0x%x)", - object_get_typename(obj), prev_val); - return; - } - - cpu->cfg.mvendorid =3D value; -} - -static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint32_t value =3D RISCV_CPU(obj)->cfg.mvendorid; - - visit_type_uint32(v, name, &value, errp); -} - static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2114,9 +2122,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, - cpu_set_mvendorid, NULL, NULL); - object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, cpu_set_mimpid, NULL, NULL); =20 --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:41:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303672; x=1704908472; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NKIuukt3Nvj+XBBcPV8KJ+jhjW9YHguYxnCbdEtqjhw=; b=UkDKvKgchoOrOnminPjm8GV/atK6FX6VUx76BxHsNhDCxdgAg8y+p1Gua4Lxh8gXan IisMYevXI06vQy64ecp9ywGf7fDKNvNE43T1arHM/JpqphYysbwVBN8c9nY2NZTzoIZo fG1CPTPz0YWKaX6ApMg6+ZWKz16Eit6H0sTy3arpT2eJp9w6c4XmaKOaOYxmP86yDy5c 7hiyQnPV3Csic2ctaQkdStFZSw7WasqDHNSIW6lGJy8IyPuQgeA/4wMEVSYFCtrbdU/U nBG2Fox059NKKZWsh91Z0AoxWvYOSFdgPZH87d0fSzXmuC054Ah5eiRYrDeFBA3nwg7F bZcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303672; x=1704908472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NKIuukt3Nvj+XBBcPV8KJ+jhjW9YHguYxnCbdEtqjhw=; b=SdNJ/OHfQtcN0Ud5qa4mb4P5k/MlrFGnsVmoRZMB/hpk+BA9UIz5i6OEciFJJ0msqf ZiO/83aQd+0j8/XFw0HeQv25YC26/mZAIDKwkhG2ublGZlvnxsvheCYW+wU3Wt9Ez9jr LDqAqK7t1bf62rZymu+l0p1YNkK5RqD1V+BIrBGyeacL1LKjOE790y5HEOKl397mJYF4 BpZ5U4wQzQa6MnPagIu+2VNNa7hMGdxYjZXfU1+B4XlfLYmOwyzIC6hGQpm8OYl+eKjF 0XB0ziBqJ7up7WoMWKStZO7tbI/61cGET83o08AveYPuWd4dz3GaJK9j0Uud6cbgcfJt 4ZFA== X-Gm-Message-State: AOJu0YyNUhP/1z7GpW8N3NCv3vGcrVBHSKdFy1n2s8hj5Mqx2GgCDffq fWXXFmYXtaVvP9EYXcoCWbA/Tiiarv7/TI+iomvRz2V9op05uA== X-Google-Smtp-Source: AGHT+IHm6XWGTYekTiCb8O/0nso0MsdWXWwSm3L+6nA22k5Im18Y1mNrA0mxUw/sOm/WJPjSoN3enA== X-Received: by 2002:a05:6a00:1acf:b0:6d9:ab70:964c with SMTP id f15-20020a056a001acf00b006d9ab70964cmr16858233pfv.67.1704303672512; Wed, 03 Jan 2024 09:41:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 15/16] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:12 -0300 Message-ID: <20240103174013.147279-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303739440100001 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 68 ++++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2fe282d0af..3ea823f5cf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1929,6 +1929,41 @@ static const PropertyInfo prop_mvendorid =3D { .set =3D prop_mvendorid_set, }; =20 +static void prop_mimpid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void prop_mimpid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_mimpid =3D { + .name =3D "mimpid", + .get =3D prop_mimpid_get, + .set =3D prop_mimpid_set, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 @@ -1948,6 +1983,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize}, =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, + {.name =3D "mimpid", .info =3D &prop_mimpid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2013,35 +2049,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.mimpid; - uint64_t value; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - cpu->cfg.mimpid =3D value; -} - -static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.mimpid; - - visit_type_uint64(v, name, &value, errp); -} - static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2122,9 +2129,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, - cpu_set_mimpid, NULL, NULL); - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, cpu_set_marchid, NULL, NULL); =20 --=20 2.43.0 From nobody Tue Nov 26 20:24:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:41:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1704303676; x=1704908476; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UF/CefTDmCNBoXHoOvJb6MgLa49HsmQNRxYOjxOKKz8=; b=Nf/AV0cP3gc2AswuKmaFy0HgT6oV2GDO+u0BsPeyVYguFaovGsMXlF/nMFbM51dAMh Mbtt6EBrALjoY9u8+LNeOnHZ63Nl0p7NNZ//RIfm6s14MU5lo1dQqEBu+UDG23oMnb6x txIIVYyV7k8Dyrsk9+PWtmCpA+aJrRsYngbYdB5VfTrcQafwSssdAJhrkd83O3aJjkxp gzw7aM3SHF5z0kn5EaeuhqOdPryqSmVyhpn1Ze1Me/otbQD2egYPder0IsG1if3J8BHO YTaU7EhIG0/nQCC/TVH9e/7L+WX2VTLfS4Hrb+j0yzn1f9TJBlBECHuRU6ZTntr4tMRq LbUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704303676; x=1704908476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UF/CefTDmCNBoXHoOvJb6MgLa49HsmQNRxYOjxOKKz8=; b=bP6u1V5ItRX0gyaWIxl+Z4VDV/3MLFIctELGjEDtqYHVdWoD6LbN50DfP8E9Lb7Tqa rm41476XnBzxvVFkn5T/N3D1raGk7pdE3bxhje8D1I3PbiVlyS4cd/ZCcplcYKxyfF0g /SaZbkPnbpb53M/RKqPv2VHlAdxEmzXAZwiRMZPCfQZLXNgzh/MRXfzy+zbmSSAsCm7F bfRj3+HIglzl9uvJ2jfi6sQwF+z8ePYFALYQ0lKwk/TpJ8bGMFY40WJ0FOtiqqXmDN0F JRZgrAASfJYL0A9cbJul0r7M0+6YCF0+hDTkB8tzGcAWsJ7NDk0WEUrXywQqFlkTXslC 869A== X-Gm-Message-State: AOJu0YxxEFL12wbffHeY7thK5aWWs9nVjKyiiNeZ9ecvP/SDPQBqs9t/ vdzh426BydybWuknmX1D0ebV4XZBmmyrEeXeVJNyJxVhDKoFSQ== X-Google-Smtp-Source: AGHT+IFh9XRFZCLmhi0GWDrFfNPXXmRetu84HJ9yjYqYlNySyev31FerDuTUMc5L70gt75IAmMy+8A== X-Received: by 2002:a05:6a00:2e20:b0:6da:14f3:53e8 with SMTP id fc32-20020a056a002e2000b006da14f353e8mr6165879pfb.24.1704303676096; Wed, 03 Jan 2024 09:41:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 16/16] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] Date: Wed, 3 Jan 2024 14:40:13 -0300 Message-ID: <20240103174013.147279-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103174013.147279-1-dbarboza@ventanamicro.com> References: <20240103174013.147279-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1704303797734100001 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 110 +++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3ea823f5cf..c67741ffa7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1964,6 +1964,62 @@ static const PropertyInfo prop_mimpid =3D { .set =3D prop_mimpid_set, }; =20 +static void prop_marchid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void prop_marchid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_marchid =3D { + .name =3D "marchid", + .get =3D prop_marchid_get, + .set =3D prop_marchid_set, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 @@ -1984,6 +2040,7 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, {.name =3D "mimpid", .info =3D &prop_mimpid}, + {.name =3D "marchid", .info =3D &prop_marchid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2049,56 +2106,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.marchid; - uint64_t value, invalid_val; - uint32_t mxlen =3D 0; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - switch (riscv_cpu_mxl(&cpu->env)) { - case MXL_RV32: - mxlen =3D 32; - break; - case MXL_RV64: - case MXL_RV128: - mxlen =3D 64; - break; - default: - g_assert_not_reached(); - } - - invalid_val =3D 1LL << (mxlen - 1); - - if (value =3D=3D invalid_val) { - error_setg(errp, "Unable to set marchid with MSB (%u) bit set " - "and the remaining bits zero", mxlen); - return; - } - - cpu->cfg.marchid =3D value; -} - -static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; - - visit_type_uint64(v, name, &value, errp); -} - static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2129,9 +2136,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, - cpu_set_marchid, NULL, NULL); - device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.43.0