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Sun, 31 Dec 2023 01:39:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IE2tFK7sUyg7wDGvXjjyi8geMiVbKY9vNMa6uu9CtDl9wZwS9RPXWNPemtQUJjKnvlCqPSEpg== X-Received: by 2002:a5d:5692:0:b0:336:67e9:ebe8 with SMTP id f18-20020a5d5692000000b0033667e9ebe8mr9281565wrv.90.1704015576333; Sun, 31 Dec 2023 01:39:36 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: kraxel@redhat.com Subject: [PATCH 6/8] vga: reindent memory access code Date: Sun, 31 Dec 2023 10:39:16 +0100 Message-ID: <20231231093918.239549-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231231093918.239549-1-pbonzini@redhat.com> References: <20231231093918.239549-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.667, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1704015678613100003 Content-Type: text/plain; charset="utf-8" The next patch will reuse latched memory access in text modes. Start with a patch that moves the latched access code out of the "if". Best reviewed with "git diff -b". Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/display/vga.c | 211 ++++++++++++++++++++++++----------------------- 1 file changed, 110 insertions(+), 101 deletions(-) diff --git a/hw/display/vga.c b/hw/display/vga.c index 2467f3f6c65..08ba5bb1118 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -832,37 +832,41 @@ uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr) } =20 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) { - /* chain 4 mode : simplest access */ + /* chain 4 mode : simplest access (but it should use the same + * algorithms as below; see e.g. vga_mem_writeb's plane mask check= ). + */ assert(addr < s->vram_size); - ret =3D s->vram_ptr[addr]; - } else if (s->gr[VGA_GFX_MODE] & 0x10) { + return s->vram_ptr[addr]; + } + + if (s->gr[VGA_GFX_MODE] & 0x10) { /* odd/even mode (aka text mode mapping) */ plane =3D (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); addr =3D ((addr & ~1) << 1) | plane; if (addr >=3D s->vram_size) { return 0xff; } - ret =3D s->vram_ptr[addr]; - } else { - /* standard VGA latched access */ - if (addr * sizeof(uint32_t) >=3D s->vram_size) { - return 0xff; - } - s->latch =3D ((uint32_t *)s->vram_ptr)[addr]; - - if (!(s->gr[VGA_GFX_MODE] & 0x08)) { - /* read mode 0 */ - plane =3D s->gr[VGA_GFX_PLANE_READ]; - ret =3D GET_PLANE(s->latch, plane); - } else { - /* read mode 1 */ - ret =3D (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) & - mask16[s->gr[VGA_GFX_COMPARE_MASK]]; - ret |=3D ret >> 16; - ret |=3D ret >> 8; - ret =3D (~ret) & 0xff; - } + return s->vram_ptr[addr]; } + + /* standard VGA latched access */ + plane =3D s->gr[VGA_GFX_PLANE_READ]; + if (addr * sizeof(uint32_t) >=3D s->vram_size) { + return 0xff; + } + s->latch =3D ((uint32_t *)s->vram_ptr)[addr]; + if (!(s->gr[VGA_GFX_MODE] & 0x08)) { + /* read mode 0 */ + ret =3D GET_PLANE(s->latch, plane); + } else { + /* read mode 1 */ + ret =3D (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) & + mask16[s->gr[VGA_GFX_COMPARE_MASK]]; + ret |=3D ret >> 16; + ret |=3D ret >> 8; + ret =3D (~ret) & 0xff; + } + return ret; } =20 @@ -912,7 +916,10 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, ui= nt32_t val) s->plane_updated |=3D mask; /* only used to detect font change= */ memory_region_set_dirty(&s->vram, addr, 1); } - } else if (s->gr[VGA_GFX_MODE] & 0x10) { + return; + } + + if (s->gr[VGA_GFX_MODE] & 0x10) { /* odd/even mode (aka text mode mapping) */ plane =3D (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); mask =3D (1 << plane); @@ -928,84 +935,86 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, u= int32_t val) s->plane_updated |=3D mask; /* only used to detect font change= */ memory_region_set_dirty(&s->vram, addr, 1); } - } else { - /* standard VGA latched access */ - write_mode =3D s->gr[VGA_GFX_MODE] & 3; - switch(write_mode) { - default: - case 0: - /* rotate */ - b =3D s->gr[VGA_GFX_DATA_ROTATE] & 7; - val =3D ((val >> b) | (val << (8 - b))) & 0xff; - val |=3D val << 8; - val |=3D val << 16; - - /* apply set/reset mask */ - set_mask =3D mask16[s->gr[VGA_GFX_SR_ENABLE]]; - val =3D (val & ~set_mask) | - (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask); - bit_mask =3D s->gr[VGA_GFX_BIT_MASK]; - break; - case 1: - val =3D s->latch; - goto do_write; - case 2: - val =3D mask16[val & 0x0f]; - bit_mask =3D s->gr[VGA_GFX_BIT_MASK]; - break; - case 3: - /* rotate */ - b =3D s->gr[VGA_GFX_DATA_ROTATE] & 7; - val =3D (val >> b) | (val << (8 - b)); - - bit_mask =3D s->gr[VGA_GFX_BIT_MASK] & val; - val =3D mask16[s->gr[VGA_GFX_SR_VALUE]]; - break; - } - - /* apply logical operation */ - func_select =3D s->gr[VGA_GFX_DATA_ROTATE] >> 3; - switch(func_select) { - case 0: - default: - /* nothing to do */ - break; - case 1: - /* and */ - val &=3D s->latch; - break; - case 2: - /* or */ - val |=3D s->latch; - break; - case 3: - /* xor */ - val ^=3D s->latch; - break; - } - - /* apply bit mask */ - bit_mask |=3D bit_mask << 8; - bit_mask |=3D bit_mask << 16; - val =3D (val & bit_mask) | (s->latch & ~bit_mask); - - do_write: - /* mask data according to sr[2] */ - mask =3D sr(s, VGA_SEQ_PLANE_WRITE); - s->plane_updated |=3D mask; /* only used to detect font change */ - write_mask =3D mask16[mask]; - if (addr * sizeof(uint32_t) >=3D s->vram_size) { - return; - } - ((uint32_t *)s->vram_ptr)[addr] =3D - (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | - (val & write_mask); -#ifdef DEBUG_VGA_MEM - printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=3D0x%08x val=3D0x%= 08x\n", - addr * 4, write_mask, val); -#endif - memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); + return; } + + mask =3D sr(s, VGA_SEQ_PLANE_WRITE); + + /* standard VGA latched access */ + write_mode =3D s->gr[VGA_GFX_MODE] & 3; + switch(write_mode) { + default: + case 0: + /* rotate */ + b =3D s->gr[VGA_GFX_DATA_ROTATE] & 7; + val =3D ((val >> b) | (val << (8 - b))) & 0xff; + val |=3D val << 8; + val |=3D val << 16; + + /* apply set/reset mask */ + set_mask =3D mask16[s->gr[VGA_GFX_SR_ENABLE]]; + val =3D (val & ~set_mask) | + (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask); + bit_mask =3D s->gr[VGA_GFX_BIT_MASK]; + break; + case 1: + val =3D s->latch; + goto do_write; + case 2: + val =3D mask16[val & 0x0f]; + bit_mask =3D s->gr[VGA_GFX_BIT_MASK]; + break; + case 3: + /* rotate */ + b =3D s->gr[VGA_GFX_DATA_ROTATE] & 7; + val =3D (val >> b) | (val << (8 - b)); + + bit_mask =3D s->gr[VGA_GFX_BIT_MASK] & val; + val =3D mask16[s->gr[VGA_GFX_SR_VALUE]]; + break; + } + + /* apply logical operation */ + func_select =3D s->gr[VGA_GFX_DATA_ROTATE] >> 3; + switch(func_select) { + case 0: + default: + /* nothing to do */ + break; + case 1: + /* and */ + val &=3D s->latch; + break; + case 2: + /* or */ + val |=3D s->latch; + break; + case 3: + /* xor */ + val ^=3D s->latch; + break; + } + + /* apply bit mask */ + bit_mask |=3D bit_mask << 8; + bit_mask |=3D bit_mask << 16; + val =3D (val & bit_mask) | (s->latch & ~bit_mask); + +do_write: + /* mask data according to sr[2] */ + s->plane_updated |=3D mask; /* only used to detect font change */ + write_mask =3D mask16[mask]; + if (addr * sizeof(uint32_t) >=3D s->vram_size) { + return; + } + ((uint32_t *)s->vram_ptr)[addr] =3D + (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | + (val & write_mask); +#ifdef DEBUG_VGA_MEM + printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=3D0x%08x val=3D0x%08x\= n", + addr * 4, write_mask, val); +#endif + memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); } =20 typedef void *vga_draw_line_func(VGACommonState *s1, uint8_t *d, --=20 2.43.0