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Sun, 31 Dec 2023 00:46:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IFMWCwk/b4PhZOvRHY0RgnNYyBDe01HR0aJUK1n0F0q/TUqJyUfeO6ZekGNAfYwHKDsL8hY9w== X-Received: by 2002:a7b:cd94:0:b0:40d:85ba:9671 with SMTP id y20-20020a7bcd94000000b0040d85ba9671mr432557wmj.86.1704012364904; Sun, 31 Dec 2023 00:46:04 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 21/46] target/i386: introduce flags writeback mechanism Date: Sun, 31 Dec 2023 09:44:37 +0100 Message-ID: <20231231084502.235366-22-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231231084502.235366-1-pbonzini@redhat.com> References: <20231231084502.235366-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.667, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1704012663100100001 Content-Type: text/plain; charset="utf-8" ALU instructions can write to both memory and flags. If the CC_SRC* and CC_DST locations have been written already when a memory access causes a fault, the value in CC_SRC* and CC_DST might be interpreted with the wrong CC_OP (the one that is in effect before the instruction. Besides just using the wrong result for the flags, something like subtracting -1 can have disastrous effects if the current CC_OP is CC_OP_EFLAGS: this is because QEMU does not expect bits outside the ALU flags to be set in CC_SRC, and env->eflags can end up set to all-ones. In the case of the attached testcase, this sets IOPL to 3 and would cause an assertion failure if SUB is moved to the new decoder. This mechanism is not really needed for BMI instructions, which can only write to a register, but put it to use anyway for cleanliness. In the case of BZHI, the code has to be modified slightly to ensure that decode->cc_src is written, otherwise the new assertions trigger. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 1 + target/i386/tcg/decode-new.c.inc | 34 +++++++++++++++++++++++++++++ target/i386/tcg/decode-new.h | 4 ++++ target/i386/tcg/emit.c.inc | 36 ++++++++++++++++++++----------- tests/tcg/i386/Makefile.target | 2 +- tests/tcg/i386/test-flags.c | 37 ++++++++++++++++++++++++++++++++ 6 files changed, 101 insertions(+), 13 deletions(-) create mode 100644 tests/tcg/i386/test-flags.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ecdd4518c64..7f0786e8b98 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1285,6 +1285,7 @@ typedef enum { =20 CC_OP_NB, } CCOp; +QEMU_BUILD_BUG_ON(CC_OP_NB >=3D 128); =20 typedef struct SegmentCache { uint32_t selector; diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index f30889dbc0a..717d7307722 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1662,6 +1662,7 @@ static void disas_insn_new(DisasContext *s, CPUState = *cpu, int b) bool first =3D true; X86DecodedInsn decode; X86DecodeFunc decode_func =3D decode_root; + uint8_t cc_live; =20 s->has_modrm =3D false; =20 @@ -1815,6 +1816,7 @@ static void disas_insn_new(DisasContext *s, CPUState = *cpu, int b) } =20 memset(&decode, 0, sizeof(decode)); + decode.cc_op =3D -1; decode.b =3D b; if (!decode_insn(s, env, decode_func, &decode)) { goto illegal_op; @@ -1953,6 +1955,38 @@ static void disas_insn_new(DisasContext *s, CPUState= *cpu, int b) decode.e.gen(s, env, &decode); gen_writeback(s, &decode, 0, s->T0); } + + /* + * Write back flags after last memory access. Some newer ALU instruct= ions, as + * well as SSE instructions, write flags in the gen_* function, but th= at can + * cause incorrect tracking of CC_OP for instructions that write to bo= th memory + * and flags. + */ + if (decode.cc_op !=3D -1) { + if (decode.cc_dst) { + tcg_gen_mov_tl(cpu_cc_dst, decode.cc_dst); + } + if (decode.cc_src) { + tcg_gen_mov_tl(cpu_cc_src, decode.cc_src); + } + if (decode.cc_src2) { + tcg_gen_mov_tl(cpu_cc_src2, decode.cc_src2); + } + if (decode.cc_op =3D=3D CC_OP_DYNAMIC) { + tcg_gen_mov_i32(cpu_cc_op, decode.cc_op_dynamic); + } + set_cc_op(s, decode.cc_op); + cc_live =3D cc_op_live[decode.cc_op]; + } else { + cc_live =3D 0; + } + if (decode.cc_op !=3D CC_OP_DYNAMIC) { + assert(!decode.cc_op_dynamic); + assert(!!decode.cc_dst =3D=3D !!(cc_live & USES_CC_DST)); + assert(!!decode.cc_src =3D=3D !!(cc_live & USES_CC_SRC)); + assert(!!decode.cc_src2 =3D=3D !!(cc_live & USES_CC_SRC2)); + } + return; gp_fault: gen_exception_gpf(s); diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 70b6717227f..25220fc4362 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -283,6 +283,10 @@ struct X86DecodedInsn { target_ulong immediate; AddressParts mem; =20 + TCGv cc_dst, cc_src, cc_src2; + TCGv_i32 cc_op_dynamic; + int8_t cc_op; + uint8_t b; }; =20 diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 4c2006fdd09..fd120e7b9b4 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -339,6 +339,19 @@ static inline int vector_len(DisasContext *s, X86Decod= edInsn *decode) return s->vex_l ? 32 : 16; } =20 +static void prepare_update1_cc(X86DecodedInsn *decode, DisasContext *s, CC= Op op) +{ + decode->cc_dst =3D s->T0; + decode->cc_op =3D op; +} + +static void prepare_update2_cc(X86DecodedInsn *decode, DisasContext *s, CC= Op op) +{ + decode->cc_src =3D s->T1; + decode->cc_dst =3D s->T0; + decode->cc_op =3D op; +} + static void gen_store_sse(DisasContext *s, X86DecodedInsn *decode, int src= _ofs) { MemOp ot =3D decode->op[0].ot; @@ -1027,6 +1040,7 @@ static void gen_##uname(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decod VSIB_AVX(VPGATHERD, vpgatherd) VSIB_AVX(VPGATHERQ, vpgatherq) =20 +/* ADCX/ADOX do not have memory operands and can use set_cc_op. */ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_= op) { int opposite_cc_op; @@ -1089,8 +1103,7 @@ static void gen_ANDN(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) MemOp ot =3D decode->op[0].ot; =20 tcg_gen_andc_tl(s->T0, s->T1, s->T0); - gen_op_update1_cc(s); - set_cc_op(s, CC_OP_LOGICB + ot); + prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); } =20 static void gen_BEXTR(DisasContext *s, CPUX86State *env, X86DecodedInsn *d= ecode) @@ -1118,10 +1131,10 @@ static void gen_BEXTR(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decode) tcg_gen_movcond_tl(TCG_COND_LEU, s->T1, s->A0, bound, s->T1, zero); tcg_gen_andc_tl(s->T0, s->T0, s->T1); =20 - gen_op_update1_cc(s); - set_cc_op(s, CC_OP_LOGICB + ot); + prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); } =20 +/* BLSI do not have memory operands and can use set_cc_op. */ static void gen_BLSI(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { MemOp ot =3D decode->op[0].ot; @@ -1133,6 +1146,7 @@ static void gen_BLSI(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) set_cc_op(s, CC_OP_BMILGB + ot); } =20 +/* BLSMSK do not have memory operands and can use set_cc_op. */ static void gen_BLSMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *= decode) { MemOp ot =3D decode->op[0].ot; @@ -1144,6 +1158,7 @@ static void gen_BLSMSK(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode set_cc_op(s, CC_OP_BMILGB + ot); } =20 +/* BLSR do not have memory operands and can use set_cc_op. */ static void gen_BLSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { MemOp ot =3D decode->op[0].ot; @@ -1164,18 +1179,15 @@ static void gen_BZHI(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode) =20 tcg_gen_ext8u_tl(s->T1, s->T1); =20 + tcg_gen_shl_tl(s->A0, mone, s->T1); + tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); + tcg_gen_andc_tl(s->T0, s->T0, s->A0); /* * Note that since we're using BMILG (in order to get O * cleared) we need to store the inverse into C. */ - tcg_gen_setcond_tl(TCG_COND_LEU, cpu_cc_src, s->T1, bound); - - tcg_gen_shl_tl(s->A0, mone, s->T1); - tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); - tcg_gen_andc_tl(s->T0, s->T0, s->A0); - - gen_op_update1_cc(s); - set_cc_op(s, CC_OP_BMILGB + ot); + tcg_gen_setcond_tl(TCG_COND_LEU, s->T1, s->T1, bound); + prepare_update2_cc(decode, s, CC_OP_BMILGB + ot); } =20 static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *d= ecode) diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target index 3dec7c6c423..9906f9e116b 100644 --- a/tests/tcg/i386/Makefile.target +++ b/tests/tcg/i386/Makefile.target @@ -13,7 +13,7 @@ config-cc.mak: Makefile =20 I386_SRCS=3D$(notdir $(wildcard $(I386_SRC)/*.c)) ALL_X86_TESTS=3D$(I386_SRCS:.c=3D) -SKIP_I386_TESTS=3Dtest-i386-ssse3 test-avx test-3dnow test-mmx +SKIP_I386_TESTS=3Dtest-i386-ssse3 test-avx test-3dnow test-mmx test-flags X86_64_TESTS:=3D$(filter test-i386-adcox test-i386-bmi2 $(SKIP_I386_TESTS)= , $(ALL_X86_TESTS)) =20 test-i386-sse-exceptions: CFLAGS +=3D -msse4.1 -mfpmath=3Dsse diff --git a/tests/tcg/i386/test-flags.c b/tests/tcg/i386/test-flags.c new file mode 100644 index 00000000000..c379e296275 --- /dev/null +++ b/tests/tcg/i386/test-flags.c @@ -0,0 +1,37 @@ +#define _GNU_SOURCE +#include +#include +#include +#include + +volatile unsigned long flags; +volatile unsigned long flags_after; +int *addr; + +void sigsegv(int sig, siginfo_t *info, ucontext_t *uc) +{ + flags =3D uc->uc_mcontext.gregs[REG_EFL]; + mprotect(addr, 4096, PROT_READ|PROT_WRITE); +} + +int main() +{ + struct sigaction sa =3D { .sa_handler =3D (void *)sigsegv, .sa_flags = =3D SA_SIGINFO }; + sigaction(SIGSEGV, &sa, NULL); + + /* fault in the page then protect it */ + addr =3D mmap (NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANON,= -1, 0); + *addr =3D 0x1234; + mprotect(addr, 4096, PROT_READ); + + asm("# set flags to all ones \n" + "mov $-1, %%eax \n" + "movq addr, %%rdi \n" + "sahf \n" + "sub %%eax, (%%rdi) \n" + "pushf \n" + "pop flags_after(%%rip) \n" : : : "eax", "edi", "memory"); + + /* OF can have any value before the SUB instruction. */ + assert((flags & 0xff) =3D=3D 0xd7 && (flags_after & 0x8ff) =3D=3D 0x17= ); +} --=20 2.43.0