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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dd; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy2.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1703868645078100001 Content-Type: text/plain; charset="utf-8" The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO device will be implemented, its output GPIOs will be connected to the SYSCFG input GPIOs. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/Kconfig | 1 + hw/arm/stm32l4x5_soc.c | 23 ++++++++++++++++++++++- include/hw/arm/stm32l4x5_soc.h | 2 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 9c9d5bb541..e7c9470d59 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -458,6 +458,7 @@ config STM32L4X5_SOC bool select ARM_V7M select OR_IRQ + select STM32L4X5_SYSCFG select STM32L4X5_EXTI =20 config XLNX_ZYNQMP_ARM diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 08b8a4c2ed..0581f4ce30 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -37,6 +37,7 @@ #define SRAM2_SIZE (32 * KiB) =20 #define EXTI_ADDR 0x40010400 +#define SYSCFG_ADDR 0x40010000 =20 #define NUM_EXTI_IRQ 40 /* Match exti line connections with their CPU IRQ number */ @@ -81,6 +82,8 @@ static void stm32l4x5_soc_initfn(Object *obj) =20 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI); =20 + object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSC= FG); + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); s->refclk =3D qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); } @@ -158,6 +161,20 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc= , Error **errp) return; } =20 + /* System configuration controller */ + dev =3D DEVICE(&s->syscfg); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, SYSCFG_ADDR); + /* + * TODO: when the GPIO device is implemented, connect it + * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and + * GPIO_NUM_PINS. + */ + + /* EXTI device */ dev =3D DEVICE(&s->exti); if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) { return; @@ -168,6 +185,11 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc= , Error **errp) sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]= )); } =20 + for (i =3D 0; i < 16; i++) { + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, + qdev_get_gpio_in(dev, i)); + } + /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400); create_unimplemented_device("TIM3", 0x40000400, 0x400); @@ -205,7 +227,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) /* RESERVED: 0x40009800, 0x6800 */ =20 /* APB2 BUS */ - create_unimplemented_device("SYSCFG", 0x40010000, 0x30); create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0); create_unimplemented_device("COMP", 0x40010200, 0x200); /* RESERVED: 0x40010800, 0x1400 */ diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index 6cba566a31..04b1151eed 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -28,6 +28,7 @@ #include "qemu/units.h" #include "hw/qdev-core.h" #include "hw/arm/armv7m.h" +#include "hw/misc/stm32l4x5_syscfg.h" #include "hw/misc/stm32l4x5_exti.h" #include "qom/object.h" =20 @@ -43,6 +44,7 @@ struct Stm32l4x5SocState { ARMv7MState armv7m; =20 Stm32l4x5ExtiState exti; + Stm32l4x5SyscfgState syscfg; =20 MemoryRegion sram1; MemoryRegion sram2; --=20 2.43.0