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Thu, 28 Dec 2023 16:49:39 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [v2 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Date: Thu, 28 Dec 2023 16:49:25 -0800 Message-Id: <20231229004929.3842055-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231229004929.3842055-1-atishp@rivosinc.com> References: <20231229004929.3842055-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=atishp@rivosinc.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1703811025611100007 Content-Type: text/plain; charset="utf-8" mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/csr.c | 67 ++++++++++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 29 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fde7ce1a5336..283468bbc652 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -224,6 +224,15 @@ static RISCVException sscofpmf(CPURISCVState *env, int= csrno) return RISCV_EXCP_NONE; } =20 +static RISCVException sscofpmf_32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return sscofpmf(env, csrno); +} + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -4972,91 +4981,91 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 - [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT4H] =3D { "mhpmevent4h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT5H] =3D { "mhpmevent5h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT6H] =3D { "mhpmevent6h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT7H] =3D { "mhpmevent7h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT8H] =3D { "mhpmevent8h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscofpmf, read_mhpmevent= h, + [CSR_MHPMEVENT9H] =3D { "mhpmevent9h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT10H] =3D { "mhpmevent10h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT11H] =3D { "mhpmevent11h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT12H] =3D { "mhpmevent12h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT13H] =3D { "mhpmevent13h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT14H] =3D { "mhpmevent14h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT15H] =3D { "mhpmevent15h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT16H] =3D { "mhpmevent16h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT17H] =3D { "mhpmevent17h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT18H] =3D { "mhpmevent18h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT19H] =3D { "mhpmevent19h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT20H] =3D { "mhpmevent20h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT21H] =3D { "mhpmevent21h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT22H] =3D { "mhpmevent22h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT23H] =3D { "mhpmevent23h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT24H] =3D { "mhpmevent24h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT25H] =3D { "mhpmevent25h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT26H] =3D { "mhpmevent26h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT27H] =3D { "mhpmevent27h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT28H] =3D { "mhpmevent28h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT29H] =3D { "mhpmevent29h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT30H] =3D { "mhpmevent30h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscofpmf, read_mhpmeven= th, + [CSR_MHPMEVENT31H] =3D { "mhpmevent31h", sscofpmf_32, read_mhpme= venth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 --=20 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qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1703811091684100003 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07be..da3f05cd5373 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -148,6 +148,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), @@ -1296,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), + DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), @@ -1308,7 +1310,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), - MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190b9..00c34fdd3209 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -72,6 +72,7 @@ struct RISCVCPUConfig { bool ext_zihpm; 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Thu, 28 Dec 2023 16:49:42 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions Date: Thu, 28 Dec 2023 16:49:27 -0800 Message-Id: <20231229004929.3842055-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231229004929.3842055-1-atishp@rivosinc.com> References: <20231229004929.3842055-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=atishp@rivosinc.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1703811025567100005 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Signed-off-by: Atish Patra --- target/riscv/cpu.c | 1 - target/riscv/cpu.h | 6 ++++++ target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da3f05cd5373..54395f95b299 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1297,7 +1297,6 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), - DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be641..34617c4c4bab 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -319,6 +319,12 @@ struct CPUArchState { =20 target_ulong mcountinhibit; =20 + /* PMU cycle & instret privilege mode filtering */ + target_ulong mcyclecfg; + target_ulong mcyclecfgh; + target_ulong minstretcfg; + target_ulong minstretcfgh; + /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ebd7917d490a..0ee91e502e8f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -401,6 +401,10 @@ /* Machine counter-inhibit register */ #define CSR_MCOUNTINHIBIT 0x320 =20 +/* Machine counter configuration registers */ +#define CSR_MCYCLECFG 0x321 +#define CSR_MINSTRETCFG 0x322 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 @@ -431,6 +435,9 @@ #define CSR_MHPMEVENT30 0x33e #define CSR_MHPMEVENT31 0x33f =20 +#define CSR_MCYCLECFGH 0x721 +#define CSR_MINSTRETCFGH 0x722 + #define CSR_MHPMEVENT3H 0x723 #define CSR_MHPMEVENT4H 0x724 #define CSR_MHPMEVENT5H 0x725 @@ -885,6 +892,28 @@ typedef enum RISCVException { /* PMU related bits */ #define MIE_LCOFIE (1 << IRQ_PMU_OVF) =20 +#define MCYCLECFG_BIT_MINH BIT_ULL(62) +#define MCYCLECFGH_BIT_MINH BIT(30) +#define MCYCLECFG_BIT_SINH BIT_ULL(61) +#define MCYCLECFGH_BIT_SINH BIT(29) +#define MCYCLECFG_BIT_UINH BIT_ULL(60) +#define MCYCLECFGH_BIT_UINH BIT(28) +#define MCYCLECFG_BIT_VSINH BIT_ULL(59) +#define MCYCLECFGH_BIT_VSINH BIT(27) +#define MCYCLECFG_BIT_VUINH BIT_ULL(58) +#define MCYCLECFGH_BIT_VUINH BIT(26) + +#define MINSTRETCFG_BIT_MINH BIT_ULL(62) +#define MINSTRETCFGH_BIT_MINH BIT(30) +#define MINSTRETCFG_BIT_SINH BIT_ULL(61) +#define MINSTRETCFGH_BIT_SINH BIT(29) +#define MINSTRETCFG_BIT_UINH BIT_ULL(60) +#define MINSTRETCFGH_BIT_UINH BIT(28) +#define MINSTRETCFG_BIT_VSINH BIT_ULL(59) +#define MINSTRETCFGH_BIT_VSINH BIT(27) +#define MINSTRETCFG_BIT_VUINH BIT_ULL(58) +#define MINSTRETCFGH_BIT_VUINH BIT(26) + #define MHPMEVENT_BIT_OF BIT_ULL(63) #define MHPMEVENTH_BIT_OF BIT(31) #define MHPMEVENT_BIT_MINH BIT_ULL(62) --=20 2.34.1 From nobody Tue Nov 26 20:32:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 28 Dec 2023 16:49:43 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [v2 4/5] target/riscv: Add cycle & instret privilege mode filtering support Date: Thu, 28 Dec 2023 16:49:28 -0800 Message-Id: <20231229004929.3842055-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231229004929.3842055-1-atishp@rivosinc.com> References: <20231229004929.3842055-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=atishp@rivosinc.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1703811087805100003 Content-Type: text/plain; charset="utf-8" From: Kaiwen Xue QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: Atish Patra Signed-off-by: Kaiwen Xue --- target/riscv/cpu.c | 1 + target/riscv/csr.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 54395f95b299..d24f7ff8b55b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1297,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 283468bbc652..618e801a7612 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -233,6 +233,27 @@ static RISCVException sscofpmf_32(CPURISCVState *env, = int csrno) return sscofpmf(env, csrno); } =20 +static RISCVException smcntrpmf(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smcntrpmf) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException smcntrpmf_32(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smcntrpmf(env, csrno); +} + + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -818,6 +839,54 @@ static int read_hpmcounterh(CPURISCVState *env, int cs= rno, target_ulong *val) =20 #else /* CONFIG_USER_ONLY */ =20 +static int read_mcyclecfg(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mcyclecfg; + return RISCV_EXCP_NONE; +} + +static int write_mcyclecfg(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mcyclecfg =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + *val =3D env->mcyclecfgh; + return RISCV_EXCP_NONE; +} + +static int write_mcyclecfgh(CPURISCVState *env, int csrno, target_ulong va= l) +{ + env->mcyclecfgh =3D val; + return RISCV_EXCP_NONE; +} + +static int read_minstretcfg(CPURISCVState *env, int csrno, target_ulong *v= al) +{ + *val =3D env->minstretcfg; + return RISCV_EXCP_NONE; +} + +static int write_minstretcfg(CPURISCVState *env, int csrno, target_ulong v= al) +{ + env->minstretcfg =3D val; + return RISCV_EXCP_NONE; +} + +static int read_minstretcfgh(CPURISCVState *env, int csrno, target_ulong *= val) +{ + *val =3D env->minstretcfgh; + return RISCV_EXCP_NONE; +} + +static int write_minstretcfgh(CPURISCVState *env, int csrno, target_ulong = val) +{ + env->minstretcfgh =3D val; + return RISCV_EXCP_NONE; +} + static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val) { int evt_index =3D csrno - CSR_MCOUNTINHIBIT; @@ -4922,6 +4991,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_mcountinhibit, .min_priv_ver =3D PRIV_VERSION_1_11_0 }, =20 + [CSR_MCYCLECFG] =3D { "mcyclecfg", smcntrpmf, read_mcyclecfg, + write_mcyclecfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MINSTRETCFG] =3D { "minstretcfg", smcntrpmf, read_minstretcfg, + write_minstretcfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0 }, + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_mhpmevent, write_mhpmevent }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_mhpmevent, @@ -4981,6 +5057,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_mhpmevent, write_mhpmevent }, =20 + [CSR_MCYCLECFGH] =3D { "mcyclecfgh", smcntrpmf_32, read_mcyclecf= gh, + write_mcyclecfgh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MINSTRETCFGH] =3D { "minstretcfgh", smcntrpmf_32, read_minstret= cfgh, + write_minstretcfgh, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MHPMEVENT3H] =3D { "mhpmevent3h", sscofpmf_32, read_mhpmev= enth, write_mhpmeventh, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, --=20 2.34.1 From nobody Tue Nov 26 20:32:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 28 Dec 2023 16:49:44 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Cc: Atish Patra , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei , Palmer Dabbelt , qemu-riscv@nongnu.org, Weiwei Li , kaiwenxue1@gmail.com Subject: [v2 5/5] target/riscv: Implement privilege mode filtering for cycle/instret Date: Thu, 28 Dec 2023 16:49:29 -0800 Message-Id: <20231229004929.3842055-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231229004929.3842055-1-atishp@rivosinc.com> References: <20231229004929.3842055-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1703811015724100001 Content-Type: text/plain; charset="utf-8" Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode switch. This patch implements that for both cycle/instret and mhpmcounters. The first one requires Smcntrpmf while the other one requires Sscofpmf to be enabled. The cycle/instret are still computed using host ticks when icount is not enabled. Otherwise, they are computed using raw icount which is more accurate in icount mode. Signed-off-by: Atish Patra Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 11 +++++ target/riscv/cpu_helper.c | 9 +++- target/riscv/csr.c | 95 ++++++++++++++++++++++++++++++--------- target/riscv/pmu.c | 43 ++++++++++++++++++ target/riscv/pmu.h | 2 + 5 files changed, 136 insertions(+), 24 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34617c4c4bab..40d10726155b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -136,6 +136,15 @@ typedef struct PMUCTRState { target_ulong irq_overflow_left; } PMUCTRState; =20 +typedef struct PMUFixedCtrState { + /* Track cycle and icount for each privilege mode */ + uint64_t counter[4]; + uint64_t counter_prev[4]; + /* Track cycle and icount for each privilege mode when V =3D 1*/ + uint64_t counter_virt[2]; + uint64_t counter_virt_prev[2]; +} PMUFixedCtrState; + struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ @@ -334,6 +343,8 @@ struct CPUArchState { /* PMU event selector configured values for RV32 */ target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 + PMUFixedCtrState pmu_fixed_ctrs[2]; + target_ulong sscratch; target_ulong mscratch; =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e7e23b34f455..3dddb1b433e8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -715,8 +715,13 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulo= ng newpriv) { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); =20 - if (icount_enabled() && newpriv !=3D env->priv) { - riscv_itrigger_update_priv(env); + if (newpriv !=3D env->priv) { + if (icount_enabled()) { + riscv_itrigger_update_priv(env); + riscv_pmu_icount_update_priv(env, newpriv); + } else { + riscv_pmu_cycle_update_priv(env, newpriv); + } } /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 618e801a7612..9926968e8e7d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -785,32 +785,16 @@ static int write_vcsr(CPURISCVState *env, int csrno, = target_ulong val) return RISCV_EXCP_NONE; } =20 +#if defined(CONFIG_USER_ONLY) /* User Timers and Counters */ static target_ulong get_ticks(bool shift) { - int64_t val; - target_ulong result; - -#if !defined(CONFIG_USER_ONLY) - if (icount_enabled()) { - val =3D icount_get(); - } else { - val =3D cpu_get_host_ticks(); - } -#else - val =3D cpu_get_host_ticks(); -#endif - - if (shift) { - result =3D val >> 32; - } else { - result =3D val; - } + int64_t val =3D cpu_get_host_ticks(); + target_ulong result =3D shift ? val >> 32 : val; =20 return result; } =20 -#if defined(CONFIG_USER_ONLY) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { @@ -935,6 +919,70 @@ static int write_mhpmeventh(CPURISCVState *env, int cs= rno, target_ulong val) return RISCV_EXCP_NONE; } =20 +static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *en= v, + int counter_idx, + bool upper_half) +{ + uint64_t curr_val =3D 0; + target_ulong result =3D 0; + uint64_t *counter_arr =3D icount_enabled() ? env->pmu_fixed_ctrs[1].co= unter : + env->pmu_fixed_ctrs[0].counter; + uint64_t *counter_arr_virt =3D icount_enabled() ? + env->pmu_fixed_ctrs[1].counter_virt : + env->pmu_fixed_ctrs[0].counter_virt; + uint64_t cfg_val =3D 0; + + if (counter_idx =3D=3D 0) { + cfg_val =3D upper_half ? ((uint64_t)env->mcyclecfgh << 32) : + env->mcyclecfg; + } else if (counter_idx =3D=3D 2) { + cfg_val =3D upper_half ? ((uint64_t)env->minstretcfgh << 32) : + env->minstretcfg; + } else { + cfg_val =3D upper_half ? + ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) : + env->mhpmevent_val[counter_idx]; + } + + if (!cfg_val) { + if (icount_enabled()) { + curr_val =3D icount_get_raw(); + } else { + curr_val =3D cpu_get_host_ticks(); + } + goto done; + } + + if (!(cfg_val & MCYCLECFG_BIT_MINH)) { + curr_val +=3D counter_arr[PRV_M]; + } + + if (!(cfg_val & MCYCLECFG_BIT_SINH)) { + curr_val +=3D counter_arr[PRV_S]; + } + + if (!(cfg_val & MCYCLECFG_BIT_UINH)) { + curr_val +=3D counter_arr[PRV_U]; + } + + if (!(cfg_val & MCYCLECFG_BIT_VSINH)) { + curr_val +=3D counter_arr_virt[PRV_S]; + } + + if (!(cfg_val & MCYCLECFG_BIT_VUINH)) { + curr_val +=3D counter_arr_virt[PRV_U]; + } + +done: + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + result =3D upper_half ? curr_val >> 32 : curr_val; + } else { + result =3D curr_val; + } + + return result; +} + static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong v= al) { int ctr_idx =3D csrno - CSR_MCYCLE; @@ -944,7 +992,8 @@ static int write_mhpmcounter(CPURISCVState *env, int cs= rno, target_ulong val) counter->mhpmcounter_val =3D val; if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounter_prev =3D get_ticks(false); + counter->mhpmcounter_prev =3D riscv_pmu_ctr_get_fixed_counters_val= (env, + ctr_idx, f= alse); if (ctr_idx > 2) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpmctr_val =3D mhpmctr_val | @@ -971,7 +1020,8 @@ static int write_mhpmcounterh(CPURISCVState *env, int = csrno, target_ulong val) mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounterh_prev =3D get_ticks(true); + counter->mhpmcounterh_prev =3D riscv_pmu_ctr_get_fixed_counters_va= l(env, + ctr_idx, = true); if (ctr_idx > 2) { riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); } @@ -1012,7 +1062,8 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVStat= e *env, target_ulong *val, */ if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - *val =3D get_ticks(upper_half) - ctr_prev + ctr_val; + *val =3D riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_= half) - + ctr_prev + ctr_val; } else { *val =3D ctr_val; } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 0e7d58b8a5c2..8b6cc4c6bb4d 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qemu/error-report.h" +#include "qemu/timer.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" @@ -176,6 +177,48 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint= 32_t ctr_idx) return 0; } =20 +void riscv_pmu_icount_update_priv(CPURISCVState *env, target_ulong newpriv) +{ + uint64_t delta; + uint64_t *counter_arr; + uint64_t *counter_arr_prev; + uint64_t current_icount =3D icount_get_raw(); + + if (env->virt_enabled) { + counter_arr =3D env->pmu_fixed_ctrs[1].counter_virt; + counter_arr_prev =3D env->pmu_fixed_ctrs[1].counter_virt_prev; + } else { + counter_arr =3D env->pmu_fixed_ctrs[1].counter; + counter_arr_prev =3D env->pmu_fixed_ctrs[1].counter_prev; + } + + counter_arr_prev[newpriv] =3D current_icount; + delta =3D current_icount - counter_arr_prev[env->priv]; + + counter_arr[env->priv] +=3D delta; +} + +void riscv_pmu_cycle_update_priv(CPURISCVState *env, target_ulong newpriv) +{ + uint64_t delta; + uint64_t *counter_arr; + uint64_t *counter_arr_prev; + uint64_t current_host_ticks =3D cpu_get_host_ticks(); + + if (env->virt_enabled) { + counter_arr =3D env->pmu_fixed_ctrs[0].counter_virt; + counter_arr_prev =3D env->pmu_fixed_ctrs[0].counter_virt_prev; + } else { + counter_arr =3D env->pmu_fixed_ctrs[0].counter; + counter_arr_prev =3D env->pmu_fixed_ctrs[0].counter_prev; + } + + counter_arr_prev[newpriv] =3D current_host_ticks; + delta =3D current_host_ticks - counter_arr_prev[env->priv]; + + counter_arr[env->priv] +=3D delta; +} + int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) { uint32_t ctr_idx; diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 505fc850d38e..50de6031a730 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -31,3 +31,5 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_even= t_idx event_idx); void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name= ); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); +void riscv_pmu_icount_update_priv(CPURISCVState *env, target_ulong newpriv= ); +void riscv_pmu_cycle_update_priv(CPURISCVState *env, target_ulong newpriv); --=20 2.34.1